| Line 266... |
Line 266... |
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
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CSR_MCONFIGPTR = 0xf15, /**< 0xf15 - mconfigptr (r/-): Machine configuration pointer register */
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CSR_MCONFIGPTR = 0xf15 /**< 0xf15 - mconfigptr (r/-): Machine configuration pointer register */
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CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
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* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
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enum NEORV32_CSR_MSTATUS_enum {
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enum NEORV32_CSR_MSTATUS_enum {
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CSR_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
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CSR_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
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CSR_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
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CSR_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
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CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
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CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
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CSR_MSTATUS_MPP_H = 12, /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
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CSR_MSTATUS_MPP_H = 12, /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
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CSR_MSTATUS_FS_L = 13, /**< CPU mstatus CSR (13): FS_L - FPU state bit low (r/w) */
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CSR_MSTATUS_FS_H = 14, /**< CPU mstatus CSR (14): FS_H - FPU state bit high (r/w) */
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CSR_MSTATUS_TW = 21, /**< CPU mstatus CSR (21): TW - timeout wait (trigger illegal instruction exception if WFI is executed outside of m-mode when set) (r/w) */
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CSR_MSTATUS_TW = 21, /**< CPU mstatus CSR (21): TW - timeout wait (trigger illegal instruction exception if WFI is executed outside of m-mode when set) (r/w) */
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CSR_MSTATUS_SD = 31 /**< CPU mstatus CSR (31): SD - extension's state summary (set = non-clean) (r/-) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
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* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
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CSR_MISA_MXL_HI = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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CSR_MISA_MXL_HI = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
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**************************************************************************/
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enum NEORV32_CSR_MZEXT_enum {
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CSR_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension (I sub-extension) available when set (r/-) */
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CSR_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension (I sub-extension) available when set (r/-) */
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CSR_MZEXT_ZMMUL = 2, /**< CPU mzext CSR (2): Zmmul extension (M sub-extension) available when set (r/-) */
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CSR_MZEXT_ZFINX = 5, /**< CPU mzext CSR (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
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CSR_MZEXT_ZXSCNT = 6, /**< CPU mzext CSR (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
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CSR_MZEXT_ZXNOCNT = 7, /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
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CSR_MZEXT_PMP = 8, /**< CPU mzext CSR (8): PMP (physical memory protection) extension available when set (r/-) */
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CSR_MZEXT_HPM = 9, /**< CPU mzext CSR (9): HPM (hardware performance monitors) extension available when set (r/-) */
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CSR_MZEXT_DEBUGMODE = 10 /**< CPU mzext CSR (10): RISC-V CPU debug mode available when set (r/-) */
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};
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/**********************************************************************//**
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* CPU <b>mhpmevent</b> hardware performance monitor events
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* CPU <b>mhpmevent</b> hardware performance monitor events
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_HPMCNT_EVENT_enum {
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enum NEORV32_HPMCNT_EVENT_enum {
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HPMCNT_EVENT_CY = 0, /**< CPU mhpmevent CSR (0): Active cycle */
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HPMCNT_EVENT_CY = 0, /**< CPU mhpmevent CSR (0): Active cycle */
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HPMCNT_EVENT_IR = 2, /**< CPU mhpmevent CSR (2): Retired instruction */
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HPMCNT_EVENT_IR = 2, /**< CPU mhpmevent CSR (2): Retired instruction */
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#define SLINK_SIZE (16*4) // /**< SLINK address space size in bytes */
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#define SLINK_SIZE (16*4) // /**< SLINK address space size in bytes */
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/** SLINK control register (r/w) */
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/** SLINK control register (r/w) */
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#define SLINK_CT (*(IO_REG32 (SLINK_BASE + 0))) // r/w: control register
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#define SLINK_CT (*(IO_REG32 (SLINK_BASE + 0))) // r/w: control register
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/** SLINK status register (r/-) */
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/** SLINK status register (r/-) */
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#define SLINK_STATUS (*(IO_REG32 (SLINK_BASE + 16))) // r/-: status register
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#define SLINK_STATUS (*(IO_ROM32 (SLINK_BASE + 16))) // r/-: status register
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/** stream link 0 (r/w) */
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/** stream link 0 (r/w) */
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#define SLINK_CH0 (*(IO_REG32 (SLINK_BASE + 32 + 0))) // r/w: link 0
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#define SLINK_CH0 (*(IO_REG32 (SLINK_BASE + 32 + 0))) // r/w: link 0
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/** stream link 1 (r/w) */
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/** stream link 1 (r/w) */
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#define SLINK_CH1 (*(IO_REG32 (SLINK_BASE + 32 + 4))) // r/w: link 1
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#define SLINK_CH1 (*(IO_REG32 (SLINK_BASE + 32 + 4))) // r/w: link 1
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/** stream link 2 (r/w) */
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/** stream link 2 (r/w) */
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| Line 1037... |
Line 1015... |
#define GPIO_BASE (0xFFFFFFC0UL) // /**< GPIO base address */
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#define GPIO_BASE (0xFFFFFFC0UL) // /**< GPIO base address */
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/** GPIO address space size in bytes */
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/** GPIO address space size in bytes */
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#define GPIO_SIZE (4*4) // /**< GPIO address space size in bytes */
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#define GPIO_SIZE (4*4) // /**< GPIO address space size in bytes */
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/** GPIO parallel input port lower 32-bit (r/-) */
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/** GPIO parallel input port lower 32-bit (r/-) */
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#define GPIO_INPUT_LO (*(IO_REG32 (GPIO_BASE + 0)))
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#define GPIO_INPUT_LO (*(IO_ROM32 (GPIO_BASE + 0)))
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/** GPIO parallel input port upper 32-bit (r/-) */
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/** GPIO parallel input port upper 32-bit (r/-) */
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#define GPIO_INPUT_HI (*(IO_REG32 (GPIO_BASE + 4)))
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#define GPIO_INPUT_HI (*(IO_ROM32 (GPIO_BASE + 4)))
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/** GPIO parallel output port lower 32-bit (r/w) */
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/** GPIO parallel output port lower 32-bit (r/w) */
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#define GPIO_OUTPUT_LO (*(IO_REG32 (GPIO_BASE + 8)))
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#define GPIO_OUTPUT_LO (*(IO_REG32 (GPIO_BASE + 8)))
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/** GPIO parallel output port upper 32-bit (r/w) */
|
/** GPIO parallel output port upper 32-bit (r/w) */
|
#define GPIO_OUTPUT_HI (*(IO_REG32 (GPIO_BASE + 12)))
|
#define GPIO_OUTPUT_HI (*(IO_REG32 (GPIO_BASE + 12)))
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/** GPIO parallel input 64-bit access (r/-) */
|
/** GPIO parallel input 64-bit access (r/-) */
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#define GPIO_INPUT (*(IO_REG64 (&GPIO_INPUT_LO)))
|
#define GPIO_INPUT (*(IO_ROM64 (&GPIO_INPUT_LO)))
|
/** GPIO parallel output 64-bit access (r/w) */
|
/** GPIO parallel output 64-bit access (r/w) */
|
#define GPIO_OUTPUT (*(IO_REG64 (&GPIO_OUTPUT_LO)))
|
#define GPIO_OUTPUT (*(IO_REG64 (&GPIO_OUTPUT_LO)))
|
/**@}*/
|
/**@}*/
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|
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| Line 1110... |
Line 1088... |
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/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: System Configuration Info Memory (SYSINFO)
|
* @name IO Device: System Configuration Info Memory (SYSINFO)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** NEOLED base address */
|
/** SYSINFO base address */
|
#define SYSINFO_BASE (0xFFFFFFE0UL) // /**< SYSINFO base address */
|
#define SYSINFO_BASE (0xFFFFFFE0UL) // /**< SYSINFO base address */
|
/** NEOLED address space size in bytes */
|
/** SYSINFO address space size in bytes */
|
#define SYSINFO_SIZE (8*4) // /**< SYSINFO address space size in bytes */
|
#define SYSINFO_SIZE (8*4) // /**< SYSINFO address space size in bytes */
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/** SYSINFO(0): Clock speed */
|
/** SYSINFO(0): Clock speed */
|
#define SYSINFO_CLK (*(IO_ROM32 (SYSINFO_BASE + 0)))
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#define SYSINFO_CLK (*(IO_ROM32 (SYSINFO_BASE + 0)))
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/** SYSINFO(1): Custom user code (via "USER_CODE" generic) */
|
/** SYSINFO(1): CPU core features */
|
#define SYSINFO_USER_CODE (*(IO_ROM32 (SYSINFO_BASE + 4)))
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#define SYSINFO_CPU (*(IO_ROM32 (SYSINFO_BASE + 4)))
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/** SYSINFO(2): Clock speed */
|
/** SYSINFO(2): Processor/SoC features */
|
#define SYSINFO_FEATURES (*(IO_ROM32 (SYSINFO_BASE + 8)))
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#define SYSINFO_FEATURES (*(IO_ROM32 (SYSINFO_BASE + 8)))
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/** SYSINFO(3): Cache configuration */
|
/** SYSINFO(3): Cache configuration */
|
#define SYSINFO_CACHE (*(IO_ROM32 (SYSINFO_BASE + 12)))
|
#define SYSINFO_CACHE (*(IO_ROM32 (SYSINFO_BASE + 12)))
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/** SYSINFO(4): Instruction memory address space base */
|
/** SYSINFO(4): Instruction memory address space base */
|
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 (SYSINFO_BASE + 16)))
|
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 (SYSINFO_BASE + 16)))
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| Line 1133... |
Line 1111... |
#define SYSINFO_IMEM_SIZE (*(IO_ROM32 (SYSINFO_BASE + 24)))
|
#define SYSINFO_IMEM_SIZE (*(IO_ROM32 (SYSINFO_BASE + 24)))
|
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
|
/** SYSINFO(7): Internal data memory (DMEM) size in bytes */
|
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 (SYSINFO_BASE + 28)))
|
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 (SYSINFO_BASE + 28)))
|
/**@}*/
|
/**@}*/
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|
|
|
|
|
|
/**********************************************************************//**
|
|
* SYSINFO_CPU (r/-): Implemented CPU sub-extensions/features
|
|
**************************************************************************/
|
|
enum NEORV32_SYSINFO_CPU_enum {
|
|
SYSINFO_CPU_ZICSR = 0, /**< SYSINFO_CPU (0): Zicsr extension (I sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */
|
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SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */
|
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SYSINFO_CPU_ZBB = 3, /**< SYSINFO_CPU (3): Zbb extension (B sub-extension) available when set (r/-) */
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|
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SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
|
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SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
|
|
SYSINFO_CPU_ZXNOCNT = 7, /**< SYSINFO_CPU (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
|
|
SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */
|
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SYSINFO_CPU_HPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
|
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SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */
|
|
|
|
SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */
|
|
SYSINFO_CPU_FASTSHIFT = 31 /**< SYSINFO_CPU (31): fast shifts (via FAST_SHIFT_EN generic) available when set (r/-) */
|
|
};
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* SYSINFO_FEATURES (r/-): Implemented processor devices/features
|
* SYSINFO_FEATURES (r/-): Implemented processor devices/features
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_SYSINFO_FEATURES_enum {
|
enum NEORV32_SYSINFO_FEATURES_enum {
|
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
|
SYSINFO_FEATURES_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
|
