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**************************************************************************/
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**************************************************************************/
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#define NEORV32_ARCHID 19
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#define NEORV32_ARCHID 19
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/**********************************************************************//**
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/**********************************************************************//**
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* @defgroup FIRQ_ALIASES Fast Interrupt Requests (FIRQ) Aliases (MIE, MIP, MCAUSE, RTE-ID)
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* @name Fast Interrupt Requests (FIRQ) Aliases (MIE, MIP, MCAUSE, RTE-ID)
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**************************************************************************/
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/**@{*/
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/** @name Watchdog Timer (WDT) */
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/**@{*/
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#define WDT_FIRQ_ENABLE CSR_MIE_FIRQ0E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define WDT_FIRQ_PENDING CSR_MIP_FIRQ0P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define WDT_RTE_ID RTE_TRAP_FIRQ_0 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define WDT_TRAP_CODE TRAP_CODE_FIRQ_0 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Custom Functions Subsystem (CFS) */
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/**@{*/
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#define CFS_FIRQ_ENABLE CSR_MIE_FIRQ1E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define CFS_FIRQ_PENDING CSR_MIP_FIRQ1P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define CFS_RTE_ID RTE_TRAP_FIRQ_1 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Primary Universal Asynchronous Receiver/Transmitter (UART0) */
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/**@{*/
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#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define UART0_RX_FIRQ_PENDING CSR_MIP_FIRQ2P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define UART0_RX_RTE_ID RTE_TRAP_FIRQ_2 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define UART0_RX_TRAP_CODE TRAP_CODE_FIRQ_2 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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#define UART0_TX_FIRQ_ENABLE CSR_MIE_FIRQ3E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define UART0_TX_FIRQ_PENDING CSR_MIP_FIRQ3P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define UART0_TX_RTE_ID RTE_TRAP_FIRQ_3 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define UART0_TX_TRAP_CODE TRAP_CODE_FIRQ_4 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Secondary Universal Asynchronous Receiver/Transmitter (UART1) */
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/**@{*/
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#define UART1_RX_FIRQ_ENABLE CSR_MIE_FIRQ4E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define UART1_RX_FIRQ_PENDING CSR_MIP_FIRQ4P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define UART1_RX_RTE_ID RTE_TRAP_FIRQ_4 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define UART1_RX_TRAP_CODE TRAP_CODE_FIRQ_4 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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#define UART1_TX_FIRQ_ENABLE CSR_MIE_FIRQ5E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define UART1_TX_FIRQ_PENDING CSR_MIP_FIRQ5P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define UART1_TX_RTE_ID RTE_TRAP_FIRQ_5 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define UART1_TX_TRAP_CODE TRAP_CODE_FIRQ_5 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Serial Peripheral Interface (SPI) */
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/**@{*/
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#define SPI_FIRQ_ENABLE CSR_MIE_FIRQ6E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define SPI_FIRQ_PENDING CSR_MIP_FIRQ6P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define SPI_RTE_ID RTE_TRAP_FIRQ_6 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define SPI_TRAP_CODE TRAP_CODE_FIRQ_6 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Two-Wire Interface (TWI) */
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/**@{*/
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#define TWI_FIRQ_ENABLE CSR_MIE_FIRQ7E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define TWI_FIRQ_PENDING CSR_MIP_FIRQ7P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define TWI_RTE_ID RTE_TRAP_FIRQ_7 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define TWI_TRAP_CODE TRAP_CODE_FIRQ_7 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name External Interrupt Controller (XIRQ) */
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/**@{*/
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#define XIRQ_FIRQ_ENABLE CSR_MIE_FIRQ8E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define XIRQ_FIRQ_PENDING CSR_MIP_FIRQ8P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define XIRQ_RTE_ID RTE_TRAP_FIRQ_8 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define XIRQ_TRAP_CODE TRAP_CODE_FIRQ_8 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Smart LED Controller (NEOLED) */
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/**@{*/
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#define NEOLED_FIRQ_ENABLE CSR_MIE_FIRQ9E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define NEOLED_FIRQ_PENDING CSR_MIP_FIRQ9P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define NEOLED_RTE_ID RTE_TRAP_FIRQ_9 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define NEOLED_TRAP_CODE TRAP_CODE_FIRQ_9 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/** @name Stream Link Interface (SLINK) */
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/**@{*/
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#define SLINK_RX_FIRQ_ENABLE CSR_MIE_FIRQ10E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define SLINK_RX_FIRQ_PENDING CSR_MIP_FIRQ10P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define SLINK_RX_RTE_ID RTE_TRAP_FIRQ_10 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define SLINK_RX_TRAP_CODE TRAP_CODE_FIRQ_10 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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#define SLINK_TX_FIRQ_ENABLE CSR_MIE_FIRQ11E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
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#define SLINK_TX_FIRQ_PENDING CSR_MIP_FIRQ11P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
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#define SLINK_TX_RTE_ID RTE_TRAP_FIRQ_11 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
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#define SLINK_TX_TRAP_CODE TRAP_CODE_FIRQ_11 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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* @name Address space sections
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* @name Address space sections
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** instruction memory base address (r/w/x) */
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/** instruction memory base address (r/w/x) */
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// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
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// -> configured via ispace_base_c constant in neorv32_package.vhd and available to SW via SYSCONFIG entry
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};
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};
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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* @name IO Device: Bus Monitor (BUSKEEPER)
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**************************************************************************/
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/**@{*/
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/** BUSKEEPER module prototype */
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typedef struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */
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} neorv32_buskeeper_t;
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/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */
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#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL)))
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/** BUSKEEPER control/data register bits */
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enum NEORV32_BUSKEEPER_CTRL_enum {
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BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register(0) (r/-): Bus error type: 0=device error, 1=access timeout */
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BUSKEEPER_ERR_SRC = 1, /**< BUSKEEPER control register(1) (r/-): Bus error source: 0=processor-external, 1=processor-internal */
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BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/c): Sticky error flag, clears after read */
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};
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/**@}*/
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/**********************************************************************//**
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* @name IO Device: External Interrupt Controller (XIRQ)
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* @name IO Device: External Interrupt Controller (XIRQ)
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**************************************************************************/
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**************************************************************************/
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/**@{*/
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/**@{*/
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/** XIRQ module prototype */
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/** XIRQ module prototype */
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typedef struct __attribute__((packed,aligned(4))) {
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typedef struct __attribute__((packed,aligned(4))) {
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UART_CTRL_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
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UART_CTRL_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
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UART_CTRL_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
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UART_CTRL_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
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UART_CTRL_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
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UART_CTRL_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
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UART_CTRL_CTS = 27, /**< UART control register(27) (r/-): current state of CTS input */
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UART_CTRL_CTS = 27, /**< UART control register(27) (r/-): current state of CTS input */
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UART_CTRL_EN = 28, /**< UART control register(28) (r/w): UART global enable */
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UART_CTRL_EN = 28, /**< UART control register(28) (r/w): UART global enable */
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UART_CTRL_RX_IRQ = 29, /**< UART control register(29) (r/w: RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty */
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UART_CTRL_RX_IRQ = 29, /**< UART control register(29) (r/w): RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty */
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UART_CTRL_TX_IRQ = 30, /**< UART control register(30) (r/w: TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full */
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UART_CTRL_TX_IRQ = 30, /**< UART control register(30) (r/w): TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full */
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UART_CTRL_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
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UART_CTRL_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter is busy when set */
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};
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};
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/** UART0/UART1 parity configuration */
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/** UART0/UART1 parity configuration */
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enum NEORV32_UART_PARITY_enum {
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enum NEORV32_UART_PARITY_enum {
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/** NEORV32_SYSINFO.CPU (r/-): Implemented CPU sub-extensions/features */
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/** NEORV32_SYSINFO.CPU (r/-): Implemented CPU sub-extensions/features */
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enum NEORV32_SYSINFO_CPU_enum {
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enum NEORV32_SYSINFO_CPU_enum {
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SYSINFO_CPU_ZICSR = 0, /**< SYSINFO_CPU (0): Zicsr extension (I sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZICSR = 0, /**< SYSINFO_CPU (0): Zicsr extension (I sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZBB = 3, /**< SYSINFO_CPU (3): Zbb extension (B sub-extension) available when set (r/-) */
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SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
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SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
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SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
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SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
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SYSINFO_CPU_ZXNOCNT = 7, /**< SYSINFO_CPU (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
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SYSINFO_CPU_ZICNTR = 7, /**< SYSINFO_CPU (7): Basie CPU counters available when set (r/-) */
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SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */
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SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */
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SYSINFO_CPU_HPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
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SYSINFO_CPU_ZIHPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
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SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */
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SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */
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SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */
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SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */
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SYSINFO_CPU_FASTSHIFT = 31 /**< SYSINFO_CPU (31): fast shifts (via FAST_SHIFT_EN generic) available when set (r/-) */
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SYSINFO_CPU_FASTSHIFT = 31 /**< SYSINFO_CPU (31): fast shifts (via FAST_SHIFT_EN generic) available when set (r/-) */
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};
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};
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