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Line 738... |
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/** SLINK interrupt control register bits */
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/** SLINK interrupt control register bits */
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enum NEORV32_SLINK_IRQ_enum {
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enum NEORV32_SLINK_IRQ_enum {
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SLINK_IRQ_RX_EN_LSB = 0, /**< SLINK IRQ configuration register( 0) (r/w): RX IRQ enable LSB (link 0) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_RX_EN_LSB = 0, /**< SLINK IRQ configuration register( 0) (r/w): RX IRQ enable LSB (link 0) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_RX_EN_MSB = 7, /**< SLINK IRQ configuration register( 7) (r/w): RX IRQ enable MSB (link 7) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_RX_EN_MSB = 7, /**< SLINK IRQ configuration register( 7) (r/w): RX IRQ enable MSB (link 7) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_RX_MODE_LSB = 8, /**< SLINK IRQ configuration register( 8) (r/w): RX IRQ mode LSB (link 0) */
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SLINK_IRQ_RX_MODE_LSB = 8, /**< SLINK IRQ configuration register( 8) (r/w): RX IRQ mode LSB (link 0) (#NEORV32_SLINK_IRQ_RX_TYPE_enum) */
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SLINK_IRQ_RX_MODE_MSB = 15, /**< SLINK IRQ configuration register(15) (r/w): RX IRQ mode MSB (link 7) */
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SLINK_IRQ_RX_MODE_MSB = 15, /**< SLINK IRQ configuration register(15) (r/w): RX IRQ mode MSB (link 7) (#NEORV32_SLINK_IRQ_RX_TYPE_enum) */
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SLINK_IRQ_TX_EN_LSB = 16, /**< SLINK IRQ configuration register(16) (r/w): TX IRQ enable LSB (link 0) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_TX_EN_LSB = 16, /**< SLINK IRQ configuration register(16) (r/w): TX IRQ enable LSB (link 0) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_TX_EN_MSB = 23, /**< SLINK IRQ configuration register(23) (r/w): TX IRQ enable MSB (link 7) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_TX_EN_MSB = 23, /**< SLINK IRQ configuration register(23) (r/w): TX IRQ enable MSB (link 7) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_TX_MODE_LSB = 24, /**< SLINK IRQ configuration register(24) (r/w): TX IRQ mode LSB (link 0) */
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SLINK_IRQ_TX_MODE_LSB = 24, /**< SLINK IRQ configuration register(24) (r/w): TX IRQ mode LSB (link 0) (#NEORV32_SLINK_IRQ_TX_TYPE_enum) */
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SLINK_IRQ_TX_MODE_MSB = 31 /**< SLINK IRQ configuration register(31) (r/w): TX IRQ mode MSB (link 7) */
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SLINK_IRQ_TX_MODE_MSB = 31 /**< SLINK IRQ configuration register(31) (r/w): TX IRQ mode MSB (link 7) (#NEORV32_SLINK_IRQ_TX_TYPE_enum) */
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};
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};
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/** SLINK interrupt configuration enable (per link) */
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/** SLINK interrupt configuration enable (per link) */
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enum NEORV32_SLINK_IRQ_EN_enum {
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enum NEORV32_SLINK_IRQ_EN_enum {
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SLINK_IRQ_DISABLE = 0, /**< '1': IRQ disabled */
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SLINK_IRQ_DISABLE = 0, /**< '1': IRQ disabled */
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SLINK_IRQ_ENABLE = 1 /**< '0': IRQ enabled */
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SLINK_IRQ_ENABLE = 1 /**< '0': IRQ enabled */
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};
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};
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/** SLINK RX interrupt configuration type (per link) */
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/** SLINK RX interrupt configuration type (per link) */
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enum NEORV32_SLINK_IRQ_RX_TYPE_enum {
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enum NEORV32_SLINK_IRQ_RX_TYPE_enum {
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SLINK_IRQ_RX_FIFO_HALF = 0, /**< '0': RX FIFO is at least half-full */
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SLINK_IRQ_RX_FIFO_HALF = 0, /**< '0': RX FIFO fill-level rises above half-full */
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SLINK_IRQ_RX_NOT_EMPTY = 1 /**< '1': RX FIFO is not empty */
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SLINK_IRQ_RX_NOT_EMPTY = 1 /**< '1': RX FIFO is not empty */
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};
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};
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/** SLINK TX interrupt configuration type (per link) */
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/** SLINK TX interrupt configuration type (per link) */
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enum NEORV32_SLINK_IRQ_TX_TYPE_enum {
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enum NEORV32_SLINK_IRQ_TX_TYPE_enum {
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SLINK_IRQ_TX_FIFO_HALF = 0, /**< '0': TX FIFO is less than half-full */
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SLINK_IRQ_TX_FIFO_HALF = 0, /**< '0': TX FIFO fill-level falls below half-full */
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SLINK_IRQ_TX_NOT_FULL = 1 /**< '1': TX FIFO is not FULL */
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SLINK_IRQ_TX_NOT_FULL = 1 /**< '1': TX FIFO is not FULL */
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};
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};
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/** SLINK status register bits */
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/** SLINK status register bits */
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enum NEORV32_SLINK_STATUS_enum {
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enum NEORV32_SLINK_STATUS_enum {
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Line 848... |
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL)))
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#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL)))
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/** BUSKEEPER control/data register bits */
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/** BUSKEEPER control/data register bits */
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enum NEORV32_BUSKEEPER_CTRL_enum {
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enum NEORV32_BUSKEEPER_CTRL_enum {
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BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register(0) (r/-): Bus error type: 0=device error, 1=access timeout */
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BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register(0) (r/-): Bus error type: 0=device error, 1=access timeout */
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BUSKEEPER_ERR_SRC = 1, /**< BUSKEEPER control register(1) (r/-): Bus error source: 0=processor-external, 1=processor-internal */
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BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/c): Sticky error flag, clears after read or write access */
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BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/c): Sticky error flag, clears after read */
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};
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};
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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Line 1031... |
TWI_CTRL_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
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TWI_CTRL_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
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TWI_CTRL_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
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TWI_CTRL_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
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TWI_CTRL_PRSC0 = 3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */
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TWI_CTRL_PRSC0 = 3, /**< TWI control register(3) (r/w): Clock prescaler select bit 0 */
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TWI_CTRL_PRSC1 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */
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TWI_CTRL_PRSC1 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 1 */
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TWI_CTRL_PRSC2 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */
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TWI_CTRL_PRSC2 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 2 */
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TWI_CTRL_MACK = 6, /**< TWI control register(6) (r/w): Generate controller ACK for each transmission */
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TWI_CTRL_MACK = 6, /**< TWI control register(6) (r/w): Generate ACK by controller for each transmission */
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TWI_CTRL_CKSTEN = 7, /**< TWI control register(7) (r/w): Enable clock stretching (by peripheral) */
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TWI_CTRL_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
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TWI_CTRL_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
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TWI_CTRL_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
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TWI_CTRL_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
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};
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};
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