| Line 1... |
Line 1... |
// #################################################################################################
|
// #################################################################################################
|
// # << NEORV32: neorv32.h - Main Core Library File >> #
|
// # << NEORV32: neorv32.h - Main Core Library File >> #
|
// # ********************************************************************************************* #
|
// # ********************************************************************************************* #
|
// # BSD 3-Clause License #
|
// # BSD 3-Clause License #
|
// # #
|
// # #
|
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
|
// # #
|
// # #
|
// # Redistribution and use in source and binary forms, with or without modification, are #
|
// # Redistribution and use in source and binary forms, with or without modification, are #
|
// # permitted provided that the following conditions are met: #
|
// # permitted provided that the following conditions are met: #
|
// # #
|
// # #
|
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
| Line 58... |
Line 58... |
* Available CPU Control and Status Registers (CSRs)
|
* Available CPU Control and Status Registers (CSRs)
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_CSR_enum {
|
enum NEORV32_CSR_enum {
|
CSR_FFLAGS = 0x001, /**< 0x001 - fflags (r/w): Floating-point accrued exception flags */
|
CSR_FFLAGS = 0x001, /**< 0x001 - fflags (r/w): Floating-point accrued exception flags */
|
CSR_FRM = 0x002, /**< 0x002 - frm (r/w): Floating-point dynamic rounding mode */
|
CSR_FRM = 0x002, /**< 0x002 - frm (r/w): Floating-point dynamic rounding mode */
|
CSR_FCSR = 0x003, /**< 0x003 - fcsr (r/w): Floating-point control/staturs register (frm + fflags) */
|
CSR_FCSR = 0x003, /**< 0x003 - fcsr (r/w): Floating-point control/status register (frm + fflags) */
|
|
|
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
|
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
|
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
|
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
|
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
|
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
|
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
|
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
|
| Line 825... |
Line 825... |
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
|
* @name IO Device: Execute In Place Module (XIP)
|
|
**************************************************************************/
|
|
/**@{*/
|
|
/** XIP module prototype */
|
|
typedef struct __attribute__((packed,aligned(4))) {
|
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_XIP_CTRL_enum) */
|
|
const uint32_t reserved; /**< offset 4: reserved */
|
|
uint32_t DATA_LO; /**< offset 8: SPI data register low */
|
|
uint32_t DATA_HI; /**< offset 12: SPI data register high */
|
|
} neorv32_xip_t;
|
|
|
|
/** XIP module hardware access (#neorv32_xip_t) */
|
|
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (0xFFFFFF40UL)))
|
|
|
|
/** XIP control/data register bits */
|
|
enum NEORV32_XIP_CTRL_enum {
|
|
XIP_CTRL_EN = 0, /**< XIP control register( 0) (r/w): XIP module enable */
|
|
XIP_CTRL_PRSC0 = 1, /**< XIP control register( 1) (r/w): Clock prescaler select bit 0 */
|
|
XIP_CTRL_PRSC1 = 2, /**< XIP control register( 2) (r/w): Clock prescaler select bit 1 */
|
|
XIP_CTRL_PRSC2 = 3, /**< XIP control register( 3) (r/w): Clock prescaler select bit 2 */
|
|
XIP_CTRL_CPOL = 4, /**< XIP control register( 4) (r/w): SPI (idle) clock polarity */
|
|
XIP_CTRL_CPHA = 5, /**< XIP control register( 5) (r/w): SPI clock phase */
|
|
XIP_CTRL_SPI_NBYTES_LSB = 6, /**< XIP control register( 6) (r/w): Number of bytes in SPI transmission, LSB */
|
|
XIP_CTRL_SPI_NBYTES_MSB = 9, /**< XIP control register( 9) (r/w): Number of bytes in SPI transmission, MSB */
|
|
XIP_CTRL_XIP_EN = 10, /**< XIP control register(10) (r/w): XIP access enable */
|
|
XIP_CTRL_XIP_ABYTES_LSB = 11, /**< XIP control register(11) (r/w): Number XIP address bytes (minus 1), LSB */
|
|
XIP_CTRL_XIP_ABYTES_MSB = 12, /**< XIP control register(12) (r/w): Number XIP address bytes (minus 1), MSB */
|
|
XIP_CTRL_RD_CMD_LSB = 13, /**< XIP control register(13) (r/w): SPI flash read command, LSB */
|
|
XIP_CTRL_RD_CMD_MSB = 20, /**< XIP control register(20) (r/w): SPI flash read command, MSB */
|
|
XIP_CTRL_PAGE_LSB = 21, /**< XIP control register(21) (r/w): XIP memory page, LSB */
|
|
XIP_CTRL_PAGE_MSB = 24, /**< XIP control register(24) (r/w): XIP memory page, MSB */
|
|
XIP_CTRL_SPI_CSEN = 25, /**< XIP control register(25) (r/w): SPI chip-select enable */
|
|
XIP_CTRL_HIGHSPEED = 26, /**< XIP control register(26) (r/w): SPI high-speed mode enable (ignoring XIP_CTRL_PRSC) */
|
|
|
|
XIP_CTRL_PHY_BUSY = 30, /**< XIP control register(20) (r/-): SPI PHY is busy */
|
|
XIP_CTRL_XIP_BUSY = 31 /**< XIP control register(31) (r/-): XIP access in progress */
|
|
};
|
|
/**@}*/
|
|
|
|
|
|
/**********************************************************************//**
|
* @name IO Device: General Purpose Timer (GPTMR)
|
* @name IO Device: General Purpose Timer (GPTMR)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** GPTMR module prototype */
|
/** GPTMR module prototype */
|
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
| Line 865... |
Line 906... |
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL)))
|
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL)))
|
|
|
/** BUSKEEPER control/data register bits */
|
/** BUSKEEPER control/data register bits */
|
enum NEORV32_BUSKEEPER_CTRL_enum {
|
enum NEORV32_BUSKEEPER_CTRL_enum {
|
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register(0) (r/-): Bus error type: 0=device error, 1=access timeout */
|
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register(0) (r/-): Bus error type: 0=device error, 1=access timeout */
|
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/c): Sticky error flag, clears after read or write access */
|
BUSKEEPER_NULL_CHECK_EN = 16, /**< BUSKEEPER control register(16) (r/w): Enable NULL address check */
|
|
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/-): Sticky error flag, clears after read or write access */
|
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
| Line 1021... |
Line 1063... |
SPI_CTRL_PRSC1 = 11, /**< SPI control register(11) (r/w): Clock prescaler select bit 1 */
|
SPI_CTRL_PRSC1 = 11, /**< SPI control register(11) (r/w): Clock prescaler select bit 1 */
|
SPI_CTRL_PRSC2 = 12, /**< SPI control register(12) (r/w): Clock prescaler select bit 2 */
|
SPI_CTRL_PRSC2 = 12, /**< SPI control register(12) (r/w): Clock prescaler select bit 2 */
|
SPI_CTRL_SIZE0 = 13, /**< SPI control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
|
SPI_CTRL_SIZE0 = 13, /**< SPI control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
|
SPI_CTRL_SIZE1 = 14, /**< SPI control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
|
SPI_CTRL_SIZE1 = 14, /**< SPI control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
|
SPI_CTRL_CPOL = 15, /**< SPI control register(15) (r/w): Clock polarity */
|
SPI_CTRL_CPOL = 15, /**< SPI control register(15) (r/w): Clock polarity */
|
|
SPI_CTRL_HIGHSPEED = 16, /**< SPI control register(16) (r/w): SPI high-speed mode enable (ignoring SPI_CTRL_PRSC) */
|
|
|
SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */
|
SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */
|
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
| Line 1120... |
Line 1163... |
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
|
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** GPIO module prototype */
|
/** GPIO module prototype */
|
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit */
|
const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit, read-only */
|
const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit */
|
const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit, read-only */
|
uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */
|
uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */
|
uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */
|
uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */
|
} neorv32_gpio_t;
|
} neorv32_gpio_t;
|
|
|
/** GPIO module hardware access (#neorv32_gpio_t) */
|
/** GPIO module hardware access (#neorv32_gpio_t) */
|
| Line 1189... |
Line 1232... |
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: System Configuration Information Memory (SYSINFO)
|
* @name IO Device: System Configuration Information Memory (SYSINFO)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** SYSINFO module prototype */
|
/** SYSINFO module prototype - whole module is read-only */
|
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
const uint32_t CLK; /**< offset 0: clock speed in Hz */
|
const uint32_t CLK; /**< offset 0: clock speed in Hz */
|
const uint32_t CPU; /**< offset 4: CPU core features (#NEORV32_SYSINFO_CPU_enum) */
|
const uint32_t CPU; /**< offset 4: CPU core features (#NEORV32_SYSINFO_CPU_enum) */
|
const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */
|
const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */
|
const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
|
const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
|
| Line 1247... |
Line 1290... |
SYSINFO_SOC_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
|
SYSINFO_SOC_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
|
SYSINFO_SOC_IO_SLINK = 25, /**< SYSINFO_FEATURES (25) (r/-): Stream link interface implemented when 1 (via SLINK_NUM_RX & SLINK_NUM_TX generics) */
|
SYSINFO_SOC_IO_SLINK = 25, /**< SYSINFO_FEATURES (25) (r/-): Stream link interface implemented when 1 (via SLINK_NUM_RX & SLINK_NUM_TX generics) */
|
SYSINFO_SOC_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
|
SYSINFO_SOC_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
|
SYSINFO_SOC_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
|
SYSINFO_SOC_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
|
SYSINFO_SOC_IO_XIRQ = 28, /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
|
SYSINFO_SOC_IO_XIRQ = 28, /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
|
SYSINFO_SOC_IO_GPTMR = 29 /**< SYSINFO_FEATURES (29) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */
|
SYSINFO_SOC_IO_GPTMR = 29, /**< SYSINFO_FEATURES (29) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */
|
|
SYSINFO_SOC_IO_XIP = 30 /**< SYSINFO_FEATURES (30) (r/-): Execute in place module implemented when 1 (via IO_XIP_EN generic) */
|
};
|
};
|
|
|
/** NEORV32_SYSINFO.CACHE (r/-): Cache configuration */
|
/** NEORV32_SYSINFO.CACHE (r/-): Cache configuration */
|
enum NEORV32_SYSINFO_CACHE_enum {
|
enum NEORV32_SYSINFO_CACHE_enum {
|
SYSINFO_CACHE_IC_BLOCK_SIZE_0 = 0, /**< SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */
|
SYSINFO_CACHE_IC_BLOCK_SIZE_0 = 0, /**< SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */
|
| Line 1300... |
Line 1344... |
#include "neorv32_spi.h"
|
#include "neorv32_spi.h"
|
#include "neorv32_trng.h"
|
#include "neorv32_trng.h"
|
#include "neorv32_twi.h"
|
#include "neorv32_twi.h"
|
#include "neorv32_uart.h"
|
#include "neorv32_uart.h"
|
#include "neorv32_wdt.h"
|
#include "neorv32_wdt.h"
|
|
#include "neorv32_xip.h"
|
#include "neorv32_xirq.h"
|
#include "neorv32_xirq.h"
|
|
|
#ifdef __cplusplus
|
#ifdef __cplusplus
|
}
|
}
|
#endif
|
#endif
|
