| Line 500... |
Line 500... |
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Trap codes from mcause CSR.
|
* Trap codes from mcause CSR.
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_EXCEPTION_CODES_enum {
|
enum NEORV32_EXCEPTION_CODES_enum {
|
TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
|
TRAP_CODE_I_MISALIGNED = 0x00000000UL, /**< 0.0: Instruction address misaligned */
|
TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */
|
TRAP_CODE_I_ACCESS = 0x00000001UL, /**< 0.1: Instruction (bus) access fault */
|
TRAP_CODE_I_ILLEGAL = 0x00000002, /**< 0.2: Illegal instruction */
|
TRAP_CODE_I_ILLEGAL = 0x00000002UL, /**< 0.2: Illegal instruction */
|
TRAP_CODE_BREAKPOINT = 0x00000003, /**< 0.3: Breakpoint (EBREAK instruction) */
|
TRAP_CODE_BREAKPOINT = 0x00000003UL, /**< 0.3: Breakpoint (EBREAK instruction) */
|
TRAP_CODE_L_MISALIGNED = 0x00000004, /**< 0.4: Load address misaligned */
|
TRAP_CODE_L_MISALIGNED = 0x00000004UL, /**< 0.4: Load address misaligned */
|
TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */
|
TRAP_CODE_L_ACCESS = 0x00000005UL, /**< 0.5: Load (bus) access fault */
|
TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */
|
TRAP_CODE_S_MISALIGNED = 0x00000006UL, /**< 0.6: Store address misaligned */
|
TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */
|
TRAP_CODE_S_ACCESS = 0x00000007UL, /**< 0.7: Store (bus) access fault */
|
TRAP_CODE_UENV_CALL = 0x00000008, /**< 0.8: Environment call from user mode (ECALL instruction) */
|
TRAP_CODE_UENV_CALL = 0x00000008UL, /**< 0.8: Environment call from user mode (ECALL instruction) */
|
TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
|
TRAP_CODE_MENV_CALL = 0x0000000bUL, /**< 0.11: Environment call from machine mode (ECALL instruction) */
|
TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */
|
TRAP_CODE_MSI = 0x80000003UL, /**< 1.3: Machine software interrupt */
|
TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */
|
TRAP_CODE_MTI = 0x80000007UL, /**< 1.7: Machine timer interrupt */
|
TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */
|
TRAP_CODE_MEI = 0x8000000bUL, /**< 1.11: Machine external interrupt */
|
TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
|
TRAP_CODE_FIRQ_0 = 0x80000010UL, /**< 1.16: Fast interrupt channel 0 */
|
TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
|
TRAP_CODE_FIRQ_1 = 0x80000011UL, /**< 1.17: Fast interrupt channel 1 */
|
TRAP_CODE_FIRQ_2 = 0x80000012, /**< 1.18: Fast interrupt channel 2 */
|
TRAP_CODE_FIRQ_2 = 0x80000012UL, /**< 1.18: Fast interrupt channel 2 */
|
TRAP_CODE_FIRQ_3 = 0x80000013, /**< 1.19: Fast interrupt channel 3 */
|
TRAP_CODE_FIRQ_3 = 0x80000013UL, /**< 1.19: Fast interrupt channel 3 */
|
TRAP_CODE_FIRQ_4 = 0x80000014, /**< 1.20: Fast interrupt channel 4 */
|
TRAP_CODE_FIRQ_4 = 0x80000014UL, /**< 1.20: Fast interrupt channel 4 */
|
TRAP_CODE_FIRQ_5 = 0x80000015, /**< 1.21: Fast interrupt channel 5 */
|
TRAP_CODE_FIRQ_5 = 0x80000015UL, /**< 1.21: Fast interrupt channel 5 */
|
TRAP_CODE_FIRQ_6 = 0x80000016, /**< 1.22: Fast interrupt channel 6 */
|
TRAP_CODE_FIRQ_6 = 0x80000016UL, /**< 1.22: Fast interrupt channel 6 */
|
TRAP_CODE_FIRQ_7 = 0x80000017, /**< 1.23: Fast interrupt channel 7 */
|
TRAP_CODE_FIRQ_7 = 0x80000017UL, /**< 1.23: Fast interrupt channel 7 */
|
TRAP_CODE_FIRQ_8 = 0x80000018, /**< 1.24: Fast interrupt channel 8 */
|
TRAP_CODE_FIRQ_8 = 0x80000018UL, /**< 1.24: Fast interrupt channel 8 */
|
TRAP_CODE_FIRQ_9 = 0x80000019, /**< 1.25: Fast interrupt channel 9 */
|
TRAP_CODE_FIRQ_9 = 0x80000019UL, /**< 1.25: Fast interrupt channel 9 */
|
TRAP_CODE_FIRQ_10 = 0x8000001a, /**< 1.26: Fast interrupt channel 10 */
|
TRAP_CODE_FIRQ_10 = 0x8000001aUL, /**< 1.26: Fast interrupt channel 10 */
|
TRAP_CODE_FIRQ_11 = 0x8000001b, /**< 1.27: Fast interrupt channel 11 */
|
TRAP_CODE_FIRQ_11 = 0x8000001bUL, /**< 1.27: Fast interrupt channel 11 */
|
TRAP_CODE_FIRQ_12 = 0x8000001c, /**< 1.28: Fast interrupt channel 12 */
|
TRAP_CODE_FIRQ_12 = 0x8000001cUL, /**< 1.28: Fast interrupt channel 12 */
|
TRAP_CODE_FIRQ_13 = 0x8000001d, /**< 1.29: Fast interrupt channel 13 */
|
TRAP_CODE_FIRQ_13 = 0x8000001dUL, /**< 1.29: Fast interrupt channel 13 */
|
TRAP_CODE_FIRQ_14 = 0x8000001e, /**< 1.30: Fast interrupt channel 14 */
|
TRAP_CODE_FIRQ_14 = 0x8000001eUL, /**< 1.30: Fast interrupt channel 14 */
|
TRAP_CODE_FIRQ_15 = 0x8000001f /**< 1.31: Fast interrupt channel 15 */
|
TRAP_CODE_FIRQ_15 = 0x8000001fUL /**< 1.31: Fast interrupt channel 15 */
|
};
|
};
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Processor clock prescaler select
|
* Processor clock prescaler select
|
| Line 662... |
Line 662... |
#define IO_BASE_ADDRESS (0xFFFFFE00UL)
|
#define IO_BASE_ADDRESS (0xFFFFFE00UL)
|
/**@}*/
|
/**@}*/
|
|
|
|
|
// ############################################################################################################################
|
// ############################################################################################################################
|
// On-Chip Debugger (should NOT be used by application software)
|
// On-Chip Debugger (should NOT be used by application software at all!)
|
// ############################################################################################################################
|
// ############################################################################################################################
|
/**@{*/
|
/**@{*/
|
/** on-chip debugger - debug module prototype */
|
/** on-chip debugger - debug module prototype */
|
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
const uint32_t CODE[32]; /**< offset 0: park loop code ROM (r/-) */
|
const uint32_t CODE[32]; /**< offset 0: park loop code ROM (r/-) */
|
| Line 676... |
Line 676... |
const uint32_t reserved2[31]; /**< offset 260..380: reserved */
|
const uint32_t reserved2[31]; /**< offset 260..380: reserved */
|
uint32_t SREG; /**< offset 384: control and status register (r/w) (#NEORV32_OCD_DM_SREG_enum) */
|
uint32_t SREG; /**< offset 384: control and status register (r/w) (#NEORV32_OCD_DM_SREG_enum) */
|
const uint32_t reserved3[31]; /**< offset 388..508: reserved */
|
const uint32_t reserved3[31]; /**< offset 388..508: reserved */
|
} neorv32_dm_t;
|
} neorv32_dm_t;
|
|
|
|
/** on-chip debugger debug module base address */
|
|
#define NEORV32_DM_BASE (0XFFFFF800UL)
|
|
|
/** on-chip debugger debug module hardware access (#neorv32_dm_t) */
|
/** on-chip debugger debug module hardware access (#neorv32_dm_t) */
|
#define NEORV32_DM (*((volatile neorv32_dm_t*) (0XFFFFF800UL)))
|
#define NEORV32_DM (*((volatile neorv32_dm_t*) (NEORV32_DM_BASE)))
|
|
|
/** on-chip debugger debug module control and status register bits */
|
/** on-chip debugger debug module control and status register bits */
|
enum NEORV32_OCD_DM_SREG_enum {
|
enum NEORV32_OCD_DM_SREG_enum {
|
OCD_DM_SREG_HALT_ACK = 0, /**< OCD.DM control and status register(0) (-/w): CPU is halted in debug mode and waits in park loop */
|
OCD_DM_SREG_HALT_ACK = 0, /**< OCD.DM control and status register(0) (-/w): CPU is halted in debug mode and waits in park loop */
|
OCD_DM_SREG_RESUME_REQ = 1, /**< OCD.DM control and status register(1) (r/-): DM requests CPU to resume */
|
OCD_DM_SREG_RESUME_REQ = 1, /**< OCD.DM control and status register(1) (r/-): DM requests CPU to resume */
|
| Line 728... |
Line 731... |
/** CFS module prototype */
|
/** CFS module prototype */
|
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
uint32_t REG[32]; /**< offset 4*0..4*31: CFS register 0..31, user-defined */
|
uint32_t REG[32]; /**< offset 4*0..4*31: CFS register 0..31, user-defined */
|
} neorv32_cfs_t;
|
} neorv32_cfs_t;
|
|
|
|
/** CFS base address */
|
|
#define NEORV32_CFS_BASE (0xFFFFFE00UL)
|
|
|
/** CFS module hardware access (#neorv32_cfs_t) */
|
/** CFS module hardware access (#neorv32_cfs_t) */
|
#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (0xFFFFFE00UL)))
|
#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (NEORV32_CFS_BASE)))
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Pulse Width Modulation Controller (PWM)
|
* @name IO Device: Pulse Width Modulation Controller (PWM)
|
| Line 743... |
Line 749... |
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_PWM_CTRL_enum) */
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_PWM_CTRL_enum) */
|
uint32_t DUTY[15]; /**< offset 4..60: duty cycle register 0..14 */
|
uint32_t DUTY[15]; /**< offset 4..60: duty cycle register 0..14 */
|
} neorv32_pwm_t;
|
} neorv32_pwm_t;
|
|
|
|
/** PWM module base address */
|
|
#define NEORV32_PWM_BASE (0xFFFFFE80UL)
|
|
|
/** PWM module hardware access (#neorv32_pwm_t) */
|
/** PWM module hardware access (#neorv32_pwm_t) */
|
#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (0xFFFFFE80UL)))
|
#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (NEORV32_PWM_BASE)))
|
|
|
/** PWM control register bits */
|
/** PWM control register bits */
|
enum NEORV32_PWM_CTRL_enum {
|
enum NEORV32_PWM_CTRL_enum {
|
PWM_CTRL_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
|
PWM_CTRL_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
|
PWM_CTRL_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
|
PWM_CTRL_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
|
| Line 771... |
Line 780... |
const uint32_t STATUS; /**< offset 16: status register (#NEORV32_SLINK_STATUS_enum) */
|
const uint32_t STATUS; /**< offset 16: status register (#NEORV32_SLINK_STATUS_enum) */
|
const uint32_t reserved2[3]; /**< offset 20..28: reserved */
|
const uint32_t reserved2[3]; /**< offset 20..28: reserved */
|
uint32_t DATA[8]; /**< offset 32..60: stream link data channel 0..7 */
|
uint32_t DATA[8]; /**< offset 32..60: stream link data channel 0..7 */
|
} neorv32_slink_t;
|
} neorv32_slink_t;
|
|
|
|
/** SLINK module base address */
|
|
#define NEORV32_SLINK_BASE (0xFFFFFEC0UL)
|
|
|
/** SLINK module hardware access (#neorv32_slink_t) */
|
/** SLINK module hardware access (#neorv32_slink_t) */
|
#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (0xFFFFFEC0UL)))
|
#define NEORV32_SLINK (*((volatile neorv32_slink_t*) (NEORV32_SLINK_BASE)))
|
|
|
/** SLINK control register bits */
|
/** SLINK control register bits */
|
enum NEORV32_SLINK_CTRL_enum {
|
enum NEORV32_SLINK_CTRL_enum {
|
SLINK_CTRL_RX_NUM0 = 0, /**< SLINK control register(0) (r/-): number of implemented RX links bit 0 */
|
SLINK_CTRL_RX_NUM0 = 0, /**< SLINK control register(0) (r/-): number of implemented RX links bit 0 */
|
SLINK_CTRL_RX_NUM1 = 1, /**< SLINK control register(1) (r/-): number of implemented RX links bit 1 */
|
SLINK_CTRL_RX_NUM1 = 1, /**< SLINK control register(1) (r/-): number of implemented RX links bit 1 */
|
| Line 883... |
Line 895... |
const uint32_t reserved; /**< offset 4: reserved */
|
const uint32_t reserved; /**< offset 4: reserved */
|
uint32_t DATA_LO; /**< offset 8: SPI data register low */
|
uint32_t DATA_LO; /**< offset 8: SPI data register low */
|
uint32_t DATA_HI; /**< offset 12: SPI data register high */
|
uint32_t DATA_HI; /**< offset 12: SPI data register high */
|
} neorv32_xip_t;
|
} neorv32_xip_t;
|
|
|
|
/** XIP module base address */
|
|
#define NEORV32_XIP_BASE (0xFFFFFF40UL)
|
|
|
/** XIP module hardware access (#neorv32_xip_t) */
|
/** XIP module hardware access (#neorv32_xip_t) */
|
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (0xFFFFFF40UL)))
|
#define NEORV32_XIP (*((volatile neorv32_xip_t*) (NEORV32_XIP_BASE)))
|
|
|
/** XIP control/data register bits */
|
/** XIP control/data register bits */
|
enum NEORV32_XIP_CTRL_enum {
|
enum NEORV32_XIP_CTRL_enum {
|
XIP_CTRL_EN = 0, /**< XIP control register( 0) (r/w): XIP module enable */
|
XIP_CTRL_EN = 0, /**< XIP control register( 0) (r/w): XIP module enable */
|
XIP_CTRL_PRSC0 = 1, /**< XIP control register( 1) (r/w): Clock prescaler select bit 0 */
|
XIP_CTRL_PRSC0 = 1, /**< XIP control register( 1) (r/w): Clock prescaler select bit 0 */
|
| Line 924... |
Line 939... |
uint32_t THRES; /**< offset 4: threshold register */
|
uint32_t THRES; /**< offset 4: threshold register */
|
uint32_t COUNT; /**< offset 8: counter register */
|
uint32_t COUNT; /**< offset 8: counter register */
|
const uint32_t reserved; /**< offset 12: reserved */
|
const uint32_t reserved; /**< offset 12: reserved */
|
} neorv32_gptmr_t;
|
} neorv32_gptmr_t;
|
|
|
|
/** GPTMR module base address */
|
|
#define NEORV32_GPTMR_BASE (0xFFFFFF60UL)
|
|
|
/** GPTMR module hardware access (#neorv32_gptmr_t) */
|
/** GPTMR module hardware access (#neorv32_gptmr_t) */
|
#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (0xFFFFFF60UL)))
|
#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (NEORV32_GPTMR_BASE)))
|
|
|
/** GPTMR control/data register bits */
|
/** GPTMR control/data register bits */
|
enum NEORV32_GPTMR_CTRL_enum {
|
enum NEORV32_GPTMR_CTRL_enum {
|
GPTMR_CTRL_EN = 0, /**< GPTIMR control register(0) (r/w): Timer unit enable */
|
GPTMR_CTRL_EN = 0, /**< GPTIMR control register(0) (r/w): Timer unit enable */
|
GPTMR_CTRL_PRSC0 = 1, /**< GPTIMR control register(1) (r/w): Clock prescaler select bit 0 */
|
GPTMR_CTRL_PRSC0 = 1, /**< GPTIMR control register(1) (r/w): Clock prescaler select bit 0 */
|
| Line 947... |
Line 965... |
/** BUSKEEPER module prototype */
|
/** BUSKEEPER module prototype */
|
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */
|
} neorv32_buskeeper_t;
|
} neorv32_buskeeper_t;
|
|
|
|
/** BUSKEEPER module base address */
|
|
#define NEORV32_BUSKEEPER_BASE (0xFFFFFF7CUL)
|
|
|
/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */
|
/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */
|
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (0xFFFFFF7CUL)))
|
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE)))
|
|
|
/** BUSKEEPER control/data register bits */
|
/** BUSKEEPER control/data register bits */
|
enum NEORV32_BUSKEEPER_CTRL_enum {
|
enum NEORV32_BUSKEEPER_CTRL_enum {
|
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register( 0) (r/-): Bus error type: 0=device error, 1=access timeout */
|
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register( 0) (r/-): Bus error type: 0=device error, 1=access timeout */
|
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/-): Sticky error flag, clears after read or write access */
|
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/-): Sticky error flag, clears after read or write access */
|
| Line 970... |
Line 991... |
uint32_t IPR; /**< offset 4: pending IRQ register /ack/clear */
|
uint32_t IPR; /**< offset 4: pending IRQ register /ack/clear */
|
uint32_t SCR; /**< offset 8: interrupt source register */
|
uint32_t SCR; /**< offset 8: interrupt source register */
|
const uint32_t reserved; /**< offset 12: reserved */
|
const uint32_t reserved; /**< offset 12: reserved */
|
} neorv32_xirq_t;
|
} neorv32_xirq_t;
|
|
|
|
/** XIRQ module base address */
|
|
#define NEORV32_XIRQ_BASE (0xFFFFFF80UL)
|
|
|
/** XIRQ module hardware access (#neorv32_xirq_t) */
|
/** XIRQ module hardware access (#neorv32_xirq_t) */
|
#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (0xFFFFFF80UL)))
|
#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (NEORV32_XIRQ_BASE)))
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Machine System Timer (MTIME)
|
* @name IO Device: Machine System Timer (MTIME)
|
| Line 987... |
Line 1011... |
uint32_t TIME_HI; /**< offset 4: time register high word */
|
uint32_t TIME_HI; /**< offset 4: time register high word */
|
uint32_t TIMECMP_LO; /**< offset 8: compare register low word */
|
uint32_t TIMECMP_LO; /**< offset 8: compare register low word */
|
uint32_t TIMECMP_HI; /**< offset 12: compare register high word */
|
uint32_t TIMECMP_HI; /**< offset 12: compare register high word */
|
} neorv32_mtime_t;
|
} neorv32_mtime_t;
|
|
|
|
/** MTIME module base address */
|
|
#define NEORV32_MTIME_BASE (0xFFFFFF90UL)
|
|
|
/** MTIME module hardware access (#neorv32_mtime_t) */
|
/** MTIME module hardware access (#neorv32_mtime_t) */
|
#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (0xFFFFFF90UL)))
|
#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (NEORV32_MTIME_BASE)))
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)
|
* @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)
|
| Line 1002... |
Line 1029... |
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */
|
uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */
|
uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */
|
} neorv32_uart0_t;
|
} neorv32_uart0_t;
|
|
|
|
/** UART0 module base address */
|
|
#define NEORV32_UART0_BASE (0xFFFFFFA0UL)
|
|
|
/** UART0 module hardware access (#neorv32_uart0_t) */
|
/** UART0 module hardware access (#neorv32_uart0_t) */
|
#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (0xFFFFFFA0UL)))
|
#define NEORV32_UART0 (*((volatile neorv32_uart0_t*) (NEORV32_UART0_BASE)))
|
|
|
/** UART1 module prototype */
|
/** UART1 module prototype */
|
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */
|
uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */
|
uint32_t DATA; /**< offset 4: data register (#NEORV32_UART_DATA_enum) */
|
} neorv32_uart1_t;
|
} neorv32_uart1_t;
|
|
|
|
/** UART1 module base address */
|
|
#define NEORV32_UART1_BASE (0xFFFFFFD0UL)
|
|
|
/** UART1 module hardware access (#neorv32_uart1_t) */
|
/** UART1 module hardware access (#neorv32_uart1_t) */
|
#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (0xFFFFFFD0UL)))
|
#define NEORV32_UART1 (*((volatile neorv32_uart1_t*) (NEORV32_UART1_BASE)))
|
|
|
/** UART0/UART1 control register bits */
|
/** UART0/UART1 control register bits */
|
enum NEORV32_UART_CTRL_enum {
|
enum NEORV32_UART_CTRL_enum {
|
UART_CTRL_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bit, bit 0) */
|
UART_CTRL_BAUD00 = 0, /**< UART control register(0) (r/w): BAUD rate config value lsb (12-bit, bit 0) */
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UART_CTRL_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bit, bit 1) */
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UART_CTRL_BAUD01 = 1, /**< UART control register(1) (r/w): BAUD rate config value (12-bit, bit 1) */
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| Line 1088... |
Line 1121... |
typedef struct __attribute__((packed,aligned(4))) {
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typedef struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_SPI_CTRL_enum) */
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_SPI_CTRL_enum) */
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uint32_t DATA; /**< offset 4: data register */
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uint32_t DATA; /**< offset 4: data register */
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} neorv32_spi_t;
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} neorv32_spi_t;
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|
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/** SPI module base address */
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#define NEORV32_SPI_BASE (0xFFFFFFA8UL)
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|
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/** SPI module hardware access (#neorv32_spi_t) */
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/** SPI module hardware access (#neorv32_spi_t) */
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#define NEORV32_SPI (*((volatile neorv32_spi_t*) (0xFFFFFFA8UL)))
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#define NEORV32_SPI (*((volatile neorv32_spi_t*) (NEORV32_SPI_BASE)))
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|
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/** SPI control register bits */
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/** SPI control register bits */
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enum NEORV32_SPI_CTRL_enum {
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enum NEORV32_SPI_CTRL_enum {
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SPI_CTRL_CS0 = 0, /**< SPI control register(0) (r/w): Direct chip select line 0 (output is low when set) */
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SPI_CTRL_CS0 = 0, /**< SPI control register(0) (r/w): Direct chip select line 0 (output is low when set) */
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SPI_CTRL_CS1 = 1, /**< SPI control register(1) (r/w): Direct chip select line 1 (output is low when set) */
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SPI_CTRL_CS1 = 1, /**< SPI control register(1) (r/w): Direct chip select line 1 (output is low when set) */
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| Line 1126... |
Line 1162... |
typedef struct __attribute__((packed,aligned(4))) {
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typedef struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_TWI_CTRL_enum) */
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_TWI_CTRL_enum) */
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uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */
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uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */
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} neorv32_twi_t;
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} neorv32_twi_t;
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|
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/** TWI module base address */
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#define NEORV32_TWI_BASE (0xFFFFFFB0UL)
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|
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/** TWI module hardware access (#neorv32_twi_t) */
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/** TWI module hardware access (#neorv32_twi_t) */
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#define NEORV32_TWI (*((volatile neorv32_twi_t*) (0xFFFFFFB0UL)))
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#define NEORV32_TWI (*((volatile neorv32_twi_t*) (NEORV32_TWI_BASE)))
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|
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/** TWI control register bits */
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/** TWI control register bits */
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enum NEORV32_TWI_CTRL_enum {
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enum NEORV32_TWI_CTRL_enum {
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TWI_CTRL_EN = 0, /**< TWI control register(0) (r/w): TWI enable */
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TWI_CTRL_EN = 0, /**< TWI control register(0) (r/w): TWI enable */
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TWI_CTRL_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
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TWI_CTRL_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
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| Line 1160... |
Line 1199... |
/** TRNG module prototype */
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/** TRNG module prototype */
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typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */
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} neorv32_trng_t;
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} neorv32_trng_t;
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|
|
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/** TRNG module base address */
|
|
#define NEORV32_TRNG_BASE (0xFFFFFFB8UL)
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|
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/** TRNG module hardware access (#neorv32_trng_t) */
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/** TRNG module hardware access (#neorv32_trng_t) */
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#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (0xFFFFFFB8UL)))
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#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (NEORV32_TRNG_BASE)))
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|
|
/** TRNG control/data register bits */
|
/** TRNG control/data register bits */
|
enum NEORV32_TRNG_CTRL_enum {
|
enum NEORV32_TRNG_CTRL_enum {
|
TRNG_CTRL_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */
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TRNG_CTRL_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */
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TRNG_CTRL_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */
|
TRNG_CTRL_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */
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| Line 1183... |
Line 1225... |
/** WDT module prototype */
|
/** WDT module prototype */
|
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */
|
uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */
|
} neorv32_wdt_t;
|
} neorv32_wdt_t;
|
|
|
|
/** WDT module base address */
|
|
#define NEORV32_WDT_BASE (0xFFFFFFBCUL)
|
|
|
/** WDT module hardware access (#neorv32_wdt_t) */
|
/** WDT module hardware access (#neorv32_wdt_t) */
|
#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (0xFFFFFFBCUL)))
|
#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (NEORV32_WDT_BASE)))
|
|
|
/** WTD control register bits */
|
/** WTD control register bits */
|
enum NEORV32_WDT_CTRL_enum {
|
enum NEORV32_WDT_CTRL_enum {
|
WDT_CTRL_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */
|
WDT_CTRL_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */
|
WDT_CTRL_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */
|
WDT_CTRL_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */
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| Line 1215... |
Line 1260... |
const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit, read-only */
|
const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit, read-only */
|
uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */
|
uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */
|
uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */
|
uint32_t OUTPUT_HI; /**< offset 12: parallel output port upper 32-bit */
|
} neorv32_gpio_t;
|
} neorv32_gpio_t;
|
|
|
|
/** GPIO module base address */
|
|
#define NEORV32_GPIO_BASE (0xFFFFFFC0UL)
|
|
|
/** GPIO module hardware access (#neorv32_gpio_t) */
|
/** GPIO module hardware access (#neorv32_gpio_t) */
|
#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (0xFFFFFFC0UL)))
|
#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (NEORV32_GPIO_BASE)))
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Smart LED Hardware Interface (NEOLED)
|
* @name IO Device: Smart LED Hardware Interface (NEOLED)
|
| Line 1230... |
Line 1278... |
typedef struct __attribute__((packed,aligned(4))) {
|
typedef struct __attribute__((packed,aligned(4))) {
|
uint32_t CTRL; /**< offset 0: control register */
|
uint32_t CTRL; /**< offset 0: control register */
|
uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */
|
uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */
|
} neorv32_neoled_t;
|
} neorv32_neoled_t;
|
|
|
|
/** NEOLED module base address */
|
|
#define NEORV32_NEOLED_BASE (0xFFFFFFD8UL)
|
|
|
/** NEOLED module hardware access (#neorv32_neoled_t) */
|
/** NEOLED module hardware access (#neorv32_neoled_t) */
|
#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (0xFFFFFFD8UL)))
|
#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (NEORV32_NEOLED_BASE)))
|
|
|
/** NEOLED control register bits */
|
/** NEOLED control register bits */
|
enum NEORV32_NEOLED_CTRL_enum {
|
enum NEORV32_NEOLED_CTRL_enum {
|
NEOLED_CTRL_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
|
NEOLED_CTRL_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
|
NEOLED_CTRL_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
|
NEOLED_CTRL_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
|
| Line 1290... |
Line 1341... |
const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */
|
const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */
|
const uint32_t IMEM_SIZE; /**< offset 24: internal instruction memory (IMEM) size in bytes */
|
const uint32_t IMEM_SIZE; /**< offset 24: internal instruction memory (IMEM) size in bytes */
|
const uint32_t DMEM_SIZE; /**< offset 28: internal data memory (DMEM) size in bytes */
|
const uint32_t DMEM_SIZE; /**< offset 28: internal data memory (DMEM) size in bytes */
|
} neorv32_sysinfo_t;
|
} neorv32_sysinfo_t;
|
|
|
|
/** SYSINFO module base address */
|
|
#define NEORV32_SYSINFO_BASE (0xFFFFFFE0UL)
|
|
|
/** SYSINFO module hardware access (#neorv32_sysinfo_t) */
|
/** SYSINFO module hardware access (#neorv32_sysinfo_t) */
|
#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (0xFFFFFFE0UL)))
|
#define NEORV32_SYSINFO (*((volatile neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE)))
|
|
|
/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */
|
/** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */
|
enum NEORV32_SYSINFO_SOC_enum {
|
enum NEORV32_SYSINFO_SOC_enum {
|
SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
|
SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
|
SYSINFO_SOC_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
|
SYSINFO_SOC_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
|
