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Line 48... |
uint64_t neorv32_cpu_get_cycle(void);
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uint64_t neorv32_cpu_get_cycle(void);
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void neorv32_cpu_set_mcycle(uint64_t value);
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void neorv32_cpu_set_mcycle(uint64_t value);
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uint64_t neorv32_cpu_get_instret(void);
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uint64_t neorv32_cpu_get_instret(void);
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void neorv32_cpu_set_minstret(uint64_t value);
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void neorv32_cpu_set_minstret(uint64_t value);
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uint64_t neorv32_cpu_get_systime(void);
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uint64_t neorv32_cpu_get_systime(void);
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void neorv32_cpu_delay_ms(uint32_t time_ms);
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void neorv32_cpu_delay_ms(int16_t time_ms);
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void __attribute__((naked)) neorv32_cpu_goto_user_mode(void);
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void __attribute__((naked)) neorv32_cpu_goto_user_mode(void);
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int neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired);
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int neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired);
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uint32_t neorv32_cpu_pmp_get_num_regions(void);
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uint32_t neorv32_cpu_pmp_get_num_regions(void);
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uint32_t neorv32_cpu_pmp_get_granularity(void);
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uint32_t neorv32_cpu_pmp_get_granularity(void);
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int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config);
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int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config);
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uint32_t neorv32_cpu_hpm_get_counters(void);
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uint32_t neorv32_cpu_hpm_get_counters(void);
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uint32_t neorv32_cpu_hpm_get_size(void);
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int neorv32_check_zextension(uint32_t);
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int neorv32_check_zextension(uint32_t);
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/**********************************************************************//**
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/**********************************************************************//**
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* Store unsigned word to address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data word (32-bit) to store.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_word(uint32_t addr, uint32_t wdata) {
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register uint32_t reg_addr = addr;
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register uint32_t reg_data = wdata;
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asm volatile ("sw %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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* Store unsigned half-word to address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data half-word (16-bit) to store.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_half(uint32_t addr, uint16_t wdata) {
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register uint32_t reg_addr = addr;
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register uint32_t reg_data = (uint32_t)wdata;
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asm volatile ("sh %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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* Store unsigned byte to address space.
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*
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data byte (8-bit) to store.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_store_unsigned_byte(uint32_t addr, uint8_t wdata) {
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register uint32_t reg_addr = addr;
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register uint32_t reg_data = (uint32_t)wdata;
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asm volatile ("sb %[da], 0(%[ad])" : : [da] "r" (reg_data), [ad] "r" (reg_addr));
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}
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/**********************************************************************//**
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* Load unsigned word from address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data word (32-bit).
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_word(uint32_t addr) {
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register uint32_t reg_addr = addr;
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register uint32_t reg_data;
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asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return (uint32_t)reg_data;
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}
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/**********************************************************************//**
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* Load unsigned half-word from address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data half-word (16-bit).
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**************************************************************************/
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inline uint16_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_half(uint32_t addr) {
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register uint32_t reg_addr = addr;
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register uint32_t reg_data;
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asm volatile ("lhu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return (uint16_t)reg_data;
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}
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/**********************************************************************//**
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* Load unsigned byte from address space.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data byte (8-bit).
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**************************************************************************/
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inline uint8_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_byte(uint32_t addr) {
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register uint32_t reg_addr = addr;
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register uint32_t reg_data;
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asm volatile ("lbu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return (uint8_t)reg_data;
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}
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/**********************************************************************//**
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* Read data from CPU configuration and status register (CSR).
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* Read data from CPU configuration and status register (CSR).
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*
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*
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* @param[in] csr_id ID of CSR to read. See #NEORV32_CSR_enum.
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* @param[in] csr_id ID of CSR to read. See #NEORV32_CSR_enum.
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* @return Read data (uint32_t).
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* @return Read data (uint32_t).
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**************************************************************************/
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**************************************************************************/
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Line 199... |
* Put CPU into "sleep" mode.
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* Put CPU into "sleep" mode.
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*
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*
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* @note This function executes the WFI insstruction.
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* @note This function executes the WFI insstruction.
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* The WFI (wait for interrupt) instruction will make the CPU stall until
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* The WFI (wait for interrupt) instruction will make the CPU stall until
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* an interupt request is detected. Interrupts have to be globally enabled
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* an interupt request is detected. Interrupts have to be globally enabled
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* and at least one external source must be enabled (e.g., the CLIC or the machine
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* and at least one external source must be enabled (like the MTI machine
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* timer) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
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* timer interrupt) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
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* this will permanently stall the CPU.
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* this will permanently stall the CPU.
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**************************************************************************/
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
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inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
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asm volatile ("wfi");
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asm volatile ("wfi");
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