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https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [sw/] [lib/] [include/] [neorv32_cpu.h] - Diff between revs 2 and 6
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| Rev 2 |
Rev 6 |
| Line 62... |
Line 62... |
**************************************************************************/
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_read(const int csr_id) {
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_read(const int csr_id) {
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register uint32_t csr_data;
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register uint32_t csr_data;
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asm volatile ("csrrw %[result], %[input_i], zero" : [result] "=r" (csr_data) : [input_i] "i" (csr_id));
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asm volatile ("csrr %[result], %[input_i]" : [result] "=r" (csr_data) : [input_i] "i" (csr_id));
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return csr_data;
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return csr_data;
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}
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}
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Line 78... |
**************************************************************************/
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_csr_write(const int csr_id, uint32_t data) {
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inline void __attribute__ ((always_inline)) neorv32_cpu_csr_write(const int csr_id, uint32_t data) {
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register uint32_t csr_data = data;
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register uint32_t csr_data = data;
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asm volatile ("csrrw zero, %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
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asm volatile ("csrw %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
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}
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}
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#endif // neorv32_cpu_h
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#endif // neorv32_cpu_h
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