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// #################################################################################################
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// #################################################################################################
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// # << NEORV32: neorv32_cpu.h - CPU Core Functions HW Driver >> #
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// # << NEORV32: neorv32_cpu.h - CPU Core Functions HW Driver >> #
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// # ********************************************************************************************* #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # BSD 3-Clause License #
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// # #
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// # #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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// # #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # permitted provided that the following conditions are met: #
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// # #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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void neorv32_cpu_set_mcycle(uint64_t value);
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void neorv32_cpu_set_mcycle(uint64_t value);
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uint64_t neorv32_cpu_get_instret(void);
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uint64_t neorv32_cpu_get_instret(void);
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void neorv32_cpu_set_minstret(uint64_t value);
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void neorv32_cpu_set_minstret(uint64_t value);
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uint64_t neorv32_cpu_get_systime(void);
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uint64_t neorv32_cpu_get_systime(void);
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void neorv32_cpu_delay_ms(uint32_t time_ms);
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void neorv32_cpu_delay_ms(uint32_t time_ms);
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void __attribute__((naked)) neorv32_cpu_goto_user_mode(void);
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uint32_t neorv32_cpu_pmp_get_num_regions(void);
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uint32_t neorv32_cpu_pmp_get_num_regions(void);
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uint32_t neorv32_cpu_pmp_get_granularity(void);
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uint32_t neorv32_cpu_pmp_get_granularity(void);
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int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config);
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int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint8_t config);
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uint32_t neorv32_cpu_hpm_get_counters(void);
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uint32_t neorv32_cpu_hpm_get_counters(void);
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uint32_t neorv32_cpu_hpm_get_size(void);
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uint32_t neorv32_cpu_hpm_get_size(void);
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/**********************************************************************//**
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/**********************************************************************//**
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* Prototype for "after-main handler". This function is called if main() returns.
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* Prototype for "after-main handler". This function is called if main() returns.
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*
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*
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* @param[in] return_code Return value of main() function.
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* @param[in] return_code Return value of main() function.
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* @return Return value is irrelevant (there is no one left to check for it...).
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**************************************************************************/
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**************************************************************************/
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extern int __neorv32_crt0_after_main(int32_t return_code) __attribute__ ((weak));
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extern void __attribute__ ((weak)) __neorv32_crt0_after_main(int32_t return_code);
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/**********************************************************************//**
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/**********************************************************************//**
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* Store unsigned word to address space if atomic access reservation is still valid.
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* Store unsigned word to address space if atomic access reservation is still valid.
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*
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*
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asm volatile ("lr.w %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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asm volatile ("lr.w %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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#else
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#else
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asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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#endif
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#endif
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return (uint32_t)reg_data;
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return reg_data;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Load unsigned word from address space.
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* Load unsigned word from address space.
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*
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*
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* @note An unaligned access address will raise an alignment exception.
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* @note An unaligned access address will raise an alignment exception.
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*
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*
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register uint32_t reg_addr = addr;
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register uint32_t reg_addr = addr;
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register uint32_t reg_data;
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register uint32_t reg_data;
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asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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asm volatile ("lw %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return (uint32_t)reg_data;
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return reg_data;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Load unsigned half-word from address space.
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* Load unsigned half-word from address space.
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* @return Read data half-word (16-bit).
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* @return Read data half-word (16-bit).
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**************************************************************************/
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**************************************************************************/
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inline uint16_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_half(uint32_t addr) {
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inline uint16_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_half(uint32_t addr) {
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register uint32_t reg_addr = addr;
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register uint32_t reg_addr = addr;
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register uint32_t reg_data;
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register uint16_t reg_data;
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asm volatile ("lhu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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asm volatile ("lhu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return (uint16_t)reg_data;
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return reg_data;
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}
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/**********************************************************************//**
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* Load signed half-word from address space.
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*
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* @note An unaligned access address will raise an alignment exception.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data half-word (16-bit).
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**************************************************************************/
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inline int16_t __attribute__ ((always_inline)) neorv32_cpu_load_signed_half(uint32_t addr) {
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register uint32_t reg_addr = addr;
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register int16_t reg_data;
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asm volatile ("lh %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return reg_data;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Load unsigned byte from address space.
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* Load unsigned byte from address space.
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* @return Read data byte (8-bit).
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* @return Read data byte (8-bit).
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**************************************************************************/
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**************************************************************************/
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inline uint8_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_byte(uint32_t addr) {
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inline uint8_t __attribute__ ((always_inline)) neorv32_cpu_load_unsigned_byte(uint32_t addr) {
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register uint32_t reg_addr = addr;
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register uint32_t reg_addr = addr;
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register uint32_t reg_data;
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register uint8_t reg_data;
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asm volatile ("lbu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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asm volatile ("lbu %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return (uint8_t)reg_data;
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return reg_data;
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}
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/**********************************************************************//**
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* Load signed byte from address space.
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*
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* @param[in] addr Address (32-bit).
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* @return Read data byte (8-bit).
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**************************************************************************/
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inline int8_t __attribute__ ((always_inline)) neorv32_cpu_load_signed_byte(uint32_t addr) {
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register uint32_t reg_addr = addr;
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register int8_t reg_data;
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asm volatile ("lb %[da], 0(%[ad])" : [da] "=r" (reg_data) : [ad] "r" (reg_addr));
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return reg_data;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Read data from CPU configuration and status register (CSR).
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* Read data from CPU configuration and status register (CSR).
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