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#ifndef neorv32_cpu_h
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#ifndef neorv32_cpu_h
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#define neorv32_cpu_h
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#define neorv32_cpu_h
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// prototypes
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// prototypes
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void neorv32_cpu_sleep(void);
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int neorv32_cpu_switch_extension(int sel, int state);
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void neorv32_cpu_eint(void);
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void neorv32_cpu_dint(void);
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int neorv32_cpu_irq_enable(uint8_t irq_sel);
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int neorv32_cpu_irq_enable(uint8_t irq_sel);
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int neorv32_cpu_irq_disable(uint8_t irq_sel);
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int neorv32_cpu_irq_disable(uint8_t irq_sel);
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void neorv32_cpu_sw_irq(void);
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void neorv32_cpu_breakpoint(void);
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void neorv32_cpu_env_call(void);
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void neorv32_cpu_delay_ms(uint32_t time_ms);
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void neorv32_cpu_delay_ms(uint32_t time_ms);
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/**********************************************************************//**
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/**********************************************************************//**
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* Read data from CPU configuration and status register (CSR).
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* Read data from CPU configuration and status register (CSR).
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register uint32_t csr_data = data;
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register uint32_t csr_data = data;
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asm volatile ("csrw %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
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asm volatile ("csrw %[input_i], %[input_j]" : : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
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}
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}
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/**********************************************************************//**
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* Put CPU into "sleep" mode.
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*
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* @note This function executes the WFI insstruction.
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* The WFI (wait for interrupt) instruction will make the CPU stall until
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* an interupt request is detected. Interrupts have to be globally enabled
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* and at least one external source must be enabled (e.g., the CLIC or the machine
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* timer) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
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* this will permanently stall the CPU.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
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asm volatile ("wfi");
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}
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/**********************************************************************//**
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* Enable global CPU interrupts (via MIE flag in mstatus CSR).
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) {
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asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));
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}
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/**********************************************************************//**
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* Disable global CPU interrupts (via MIE flag in mstatus CSR).
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) {
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asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));
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}
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/**********************************************************************//**
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* Trigger machine software interrupt.
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*
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* @note The according IRQ has to be enabled via neorv32_cpu_irq_enable(uint8_t irq_sel) and
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* global interrupts must be enabled via neorv32_cpu_eint(void) to trigger an IRQ via software.
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* The MSI becomes active after 3 clock cycles.
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_sw_irq(void) {
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asm volatile ("csrrsi zero, mip, %0" : : "i" (1 << CPU_MIP_MSIP));
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// the MSI becomes active 3 clock cycles afters issueing
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asm volatile ("nop"); // these nops are not required, they just make sure the MSI becomes active
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asm volatile ("nop"); // before the "real" next operation is executed
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}
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/**********************************************************************//**
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* Trigger breakpoint exception (via EBREAK instruction).
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_breakpoint(void) {
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asm volatile ("ebreak");
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}
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/**********************************************************************//**
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* Trigger "environment call" exception (via ECALL instruction).
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_env_call(void) {
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asm volatile ("ecall");
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}
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#endif // neorv32_cpu_h
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#endif // neorv32_cpu_h
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