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#define REG_ADDR_t3 28 /**< register 28 - according to calling convention */
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#define REG_ADDR_t3 28 /**< register 28 - according to calling convention */
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#define REG_ADDR_t4 29 /**< register 29 - according to calling convention */
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#define REG_ADDR_t4 29 /**< register 29 - according to calling convention */
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#define REG_ADDR_t5 30 /**< register 30 - according to calling convention */
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#define REG_ADDR_t5 30 /**< register 30 - according to calling convention */
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#define REG_ADDR_t6 31 /**< register 31 - according to calling convention */
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#define REG_ADDR_t6 31 /**< register 31 - according to calling convention */
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//** Construct instruction word (32-bit) for R-type instruction */
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//** Construct instruction word (32-bit) for R2-type instruction */
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#define CMD_WORD_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
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#define CMD_WORD_R2_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
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( (opcode & 0x7f) << 0 ) + \
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( (opcode & 0x7f) << 0 ) + \
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( (rd & 0x1f) << 7 ) + \
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( (rd & 0x1f) << 7 ) + \
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( (funct3 & 0x1f) << 12 ) + \
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( (rs1 & 0x1f) << 15 ) + \
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( (rs1 & 0x1f) << 15 ) + \
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( (rs2 & 0x1f) << 20 ) + \
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( (rs2 & 0x1f) << 20 ) + \
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( (funct7 & 0x7f) << 25 ) + \
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( (funct7 & 0x7f) << 25 )
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( (funct3 & 0x1f) << 12 )
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//** Construct instruction word (32-bit) for R3-type instruction */
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#define CMD_WORD_R3_TYPE(rs3, rs2, rs1, funct3, rd, opcode) \
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( (opcode & 0x7f) << 0 ) + \
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( (rd & 0x1f) << 7 ) + \
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( (funct3 & 0x1f) << 12 ) + \
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( (rs1 & 0x1f) << 15 ) + \
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( (rs2 & 0x1f) << 20 ) + \
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( (rs3 & 0x1f) << 27 )
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//** Construct instruction word (32-bit) for I-type instruction */
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//** Construct instruction word (32-bit) for I-type instruction */
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#define CMD_WORD_I_TYPE(imm12, rs1_f5, funct3, rd, opcode) \
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#define CMD_WORD_I_TYPE(imm12, rs1_f5, funct3, rd, opcode) \
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( (opcode & 0x7f) << 0 ) + \
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( (opcode & 0x7f) << 0 ) + \
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( (rd & 0x1f) << 7 ) + \
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( (rd & 0x1f) << 7 ) + \
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( (funct3 & 0x1f) << 12 ) + \
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( (rs1_f5 & 0x1f) << 15 ) + \
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( (rs1_f5 & 0x1f) << 15 ) + \
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( (imm12 & 0xfff) << 20 ) + \
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( (imm12 & 0xfff) << 20 )
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( (funct3 & 0x1f) << 12 )
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//** Construct custom R3-type instruction (4 registers, funct3, opcode) */
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#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, rd, opcode) \
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asm volatile (".word "STR(CMD_WORD_R3_TYPE(GET_REG_ADDR(rs3), GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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//** Construct custom instruction for R-type instruction */
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//** Construct custom R2-type instruction (3 registers, funct3, funct7, opcode) */
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#define CUSTOM_INSTR_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
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#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
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asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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asm volatile (".word "STR(CMD_WORD_R2_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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//** Construct custom instruction for R1-type instruction (register + 5-bit immediate/function_select) */
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//** Construct custom R1-type instruction (2 registers, funct3, funct7, funct5, opcode) */
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#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, rd, opcode) \
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#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, rd, opcode) \
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asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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asm volatile (".word "STR(CMD_WORD_R2_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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//** Construct custom instruction for I-type instruction */
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//** Construct custom I-type instruction (2 registers, funct3, imm12, opcode) */
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#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, rd, opcode) \
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#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, rd, opcode) \
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asm volatile (".word "STR(CMD_WORD_I_TYPE(imm12, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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asm volatile (".word "STR(CMD_WORD_I_TYPE(imm12, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
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/**@}*/
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/**@}*/
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#endif // neorv32_intrinsics_h
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#endif // neorv32_intrinsics_h
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