| Line 47... |
Line 47... |
* Enable specific CPU interrupt.
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* Enable specific CPU interrupt.
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*
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*
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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*
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
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return 1;
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return 1;
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| Line 65... |
Line 65... |
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/**********************************************************************//**
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/**********************************************************************//**
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* Disable specific CPU interrupt.
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* Disable specific CPU interrupt.
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*
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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|
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
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return 1;
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return 1;
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| Line 80... |
Line 80... |
return 0;
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return 0;
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}
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}
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|
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/**********************************************************************//**
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/**********************************************************************//**
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* Get cycle count from cycle[h].
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*
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* @note The cycle[h] CSR is shadowed copy of the mcycle[h] CSR.
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*
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* @return Current cycle counter (64 bit).
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**************************************************************************/
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uint64_t neorv32_cpu_get_cycle(void) {
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union {
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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} cycles;
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uint32_t tmp1, tmp2, tmp3;
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while(1) {
|
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tmp1 = neorv32_cpu_csr_read(CSR_CYCLEH);
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tmp2 = neorv32_cpu_csr_read(CSR_CYCLE);
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tmp3 = neorv32_cpu_csr_read(CSR_CYCLEH);
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if (tmp1 == tmp3) {
|
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break;
|
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}
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}
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|
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cycles.uint32[0] = tmp2;
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cycles.uint32[1] = tmp3;
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|
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return cycles.uint64;
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}
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/**********************************************************************//**
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* Set mcycle[h] counter.
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*
|
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* @param[in] value New value for mcycle[h] CSR (64-bit).
|
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**************************************************************************/
|
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void neorv32_cpu_set_mcycle(uint64_t value) {
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|
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union {
|
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uint64_t uint64;
|
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uint32_t uint32[sizeof(uint64_t)/2];
|
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} cycles;
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|
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cycles.uint64 = value;
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|
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neorv32_cpu_csr_write(CSR_MCYCLE, 0);
|
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neorv32_cpu_csr_write(CSR_MCYCLEH, cycles.uint32[1]);
|
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neorv32_cpu_csr_write(CSR_MCYCLE, cycles.uint32[0]);
|
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}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* Get retired instructions counter from instret[h].
|
|
*
|
|
* @note The instret[h] CSR is shadowed copy of the instret[h] CSR.
|
|
*
|
|
* @return Current instructions counter (64 bit).
|
|
**************************************************************************/
|
|
uint64_t neorv32_cpu_get_instret(void) {
|
|
|
|
union {
|
|
uint64_t uint64;
|
|
uint32_t uint32[sizeof(uint64_t)/2];
|
|
} cycles;
|
|
|
|
uint32_t tmp1, tmp2, tmp3;
|
|
while(1) {
|
|
tmp1 = neorv32_cpu_csr_read(CSR_INSTRETH);
|
|
tmp2 = neorv32_cpu_csr_read(CSR_INSTRET);
|
|
tmp3 = neorv32_cpu_csr_read(CSR_INSTRETH);
|
|
if (tmp1 == tmp3) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
cycles.uint32[0] = tmp2;
|
|
cycles.uint32[1] = tmp3;
|
|
|
|
return cycles.uint64;
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* Set retired instructions counter minstret[h].
|
|
*
|
|
* @param[in] value New value for mcycle[h] CSR (64-bit).
|
|
**************************************************************************/
|
|
void neorv32_cpu_set_minstret(uint64_t value) {
|
|
|
|
union {
|
|
uint64_t uint64;
|
|
uint32_t uint32[sizeof(uint64_t)/2];
|
|
} cycles;
|
|
|
|
cycles.uint64 = value;
|
|
|
|
neorv32_cpu_csr_write(CSR_MINSTRET, 0);
|
|
neorv32_cpu_csr_write(CSR_MINSTRETH, cycles.uint32[1]);
|
|
neorv32_cpu_csr_write(CSR_MINSTRET, cycles.uint32[0]);
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* Get current system time from time[h] CSR.
|
|
*
|
|
* @note This function requires the MTIME system timer to be implemented.
|
|
*
|
|
* @return Current system time (64 bit).
|
|
**************************************************************************/
|
|
uint64_t neorv32_cpu_get_systime(void) {
|
|
|
|
union {
|
|
uint64_t uint64;
|
|
uint32_t uint32[sizeof(uint64_t)/2];
|
|
} cycles;
|
|
|
|
uint32_t tmp1, tmp2, tmp3;
|
|
while(1) {
|
|
tmp1 = neorv32_cpu_csr_read(CSR_TIMEH);
|
|
tmp2 = neorv32_cpu_csr_read(CSR_TIME);
|
|
tmp3 = neorv32_cpu_csr_read(CSR_TIMEH);
|
|
if (tmp1 == tmp3) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
cycles.uint32[0] = tmp2;
|
|
cycles.uint32[1] = tmp3;
|
|
|
|
return cycles.uint64;
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
* Simple delay function (not very precise) using busy wait.
|
* Simple delay function (not very precise) using busy wait.
|
*
|
*
|
* @param[in] time_ms Time in ms to wait.
|
* @param[in] time_ms Time in ms to wait.
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_cpu_delay_ms(uint32_t time_ms) {
|
void neorv32_cpu_delay_ms(uint32_t time_ms) {
|
|
|
uint32_t clock_speed = neorv32_cpu_csr_read(CSR_MCLOCK) >> 10; // fake divide by 1000
|
uint32_t clock_speed = SYSINFO_CLK >> 10; // fake divide by 1000
|
clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
|
clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles)
|
uint32_t cnt = clock_speed * time_ms;
|
uint32_t cnt = clock_speed * time_ms;
|
|
|
// one iteration = ~30 cycles
|
// one iteration = ~30 cycles
|
while (cnt) {
|
while (cnt) {
|
