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Line 51... |
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
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(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
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return 1;
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return 1;
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}
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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| Line 69... |
Line 70... |
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE)) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
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(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
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return 1;
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return 1;
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}
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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