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Line 294... |
#else
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#else
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return 1; // A extension not implemented -Y always fail
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return 1; // A extension not implemented -Y always fail
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#endif
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#endif
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}
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}
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/**********************************************************************//**
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* Physical memory protection (PMP): Get minimal region size (granularity).
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*
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* @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs.
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*
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* @warning This function requires the PMP CPU extension.
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*
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* @return Returns minimal region size in bytes; Returns 0 on failure.
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**************************************************************************/
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uint32_t neorv32_cpu_pmp_get_granularity(void) {
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if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) == 0) {
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return 0; // PMP not implemented
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}
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// check min granulartiy
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uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
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tmp &= 0xffffff00; // disable entry 0
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neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
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neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
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uint32_t tmp_a = neorv32_cpu_csr_read(CSR_PMPADDR0);
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uint32_t i;
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// find least-significat set bit
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for (i=31; i!=0; i--) {
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if (((tmp_a >> i) & 1) == 0) {
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break;
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}
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}
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return (uint32_t)(1 << (i+1+2));
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}
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/**********************************************************************//**
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* Physical memory protection (PMP): Configure region.
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*
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* @note Using NAPOT mode - page base address has to be naturally aligned.
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*
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* @warning This function requires the PMP CPU extension.
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*
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* @param[in] index Region number (index, 0..max_regions-1).
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* @param[in] base Region base address (has to be naturally aligned!).
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* @param[in] size Region size, has to be a power of 2 (min 8 bytes or according to HW's PMP.granularity configuration).
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* @param[in] config Region configuration (attributes) byte (for PMPCFGx).
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* @return Returns 0 on success, 1 on failure.
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**************************************************************************/
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int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config) {
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if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) == 0) {
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return 1; // PMP not implemented
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}
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if (size < 8) {
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return 1; // minimal region size is 8 bytes
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}
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if ((size & (size - 1)) != 0) {
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return 1; // region size is not a power of two
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}
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// setup configuration
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uint32_t tmp;
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uint32_t config_int = ((uint32_t)config) << ((index%4)*8);
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uint32_t config_mask = ((uint32_t)0xFF) << ((index%4)*8);
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config_mask = ~config_mask;
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// clear old configuration
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if (index < 3) {
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tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
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tmp &= config_mask; // clear old config
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neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
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}
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else {
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tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);
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tmp &= config_mask; // clear old config
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neorv32_cpu_csr_write(CSR_PMPCFG1, tmp);
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}
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// set base address and region size
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uint32_t addr_mask = ~((size - 1) >> 2);
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uint32_t size_mask = (size - 1) >> 3;
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tmp = base & addr_mask;
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tmp = tmp | size_mask;
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switch(index & 7) {
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case 0: neorv32_cpu_csr_write(CSR_PMPADDR0, tmp); break;
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case 1: neorv32_cpu_csr_write(CSR_PMPADDR1, tmp); break;
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case 2: neorv32_cpu_csr_write(CSR_PMPADDR2, tmp); break;
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case 3: neorv32_cpu_csr_write(CSR_PMPADDR3, tmp); break;
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case 4: neorv32_cpu_csr_write(CSR_PMPADDR4, tmp); break;
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case 5: neorv32_cpu_csr_write(CSR_PMPADDR5, tmp); break;
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case 6: neorv32_cpu_csr_write(CSR_PMPADDR6, tmp); break;
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case 7: neorv32_cpu_csr_write(CSR_PMPADDR7, tmp); break;
|
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default: break;
|
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}
|
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|
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// wait for HW to computer PMP-internal stuff (address masks)
|
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for (tmp=0; tmp<16; tmp++) {
|
|
asm volatile ("nop");
|
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}
|
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|
|
// set new configuration
|
|
if (index < 3) {
|
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tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
|
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tmp |= config_int; // set new config
|
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neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
|
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}
|
|
else {
|
|
tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);
|
|
tmp |= config_int; // set new config
|
|
neorv32_cpu_csr_write(CSR_PMPCFG1, tmp);
|
|
}
|
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|
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return 0;
|
|
}
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