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// #################################################################################################
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// #################################################################################################
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// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #
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// # << NEORV32: neorv32_cpu.c - CPU Core Functions HW Driver >> #
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// # ********************************************************************************************* #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # BSD 3-Clause License #
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// # #
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// # #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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// # #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # permitted provided that the following conditions are met: #
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// # #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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/**********************************************************************//**
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/**********************************************************************//**
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* Enable specific CPU interrupt.
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* Enable specific CPU interrupt.
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*
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*
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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*
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
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if ((irq_sel != CSR_MIE_MSIE) && (irq_sel != CSR_MIE_MTIE) && (irq_sel != CSR_MIE_MEIE) &&
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(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
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(irq_sel != CSR_MIE_FIRQ0E) && (irq_sel != CSR_MIE_FIRQ1E) && (irq_sel != CSR_MIE_FIRQ2E) && (irq_sel != CSR_MIE_FIRQ3E)) {
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return 1;
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return 1;
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}
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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| Line 65... |
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/**********************************************************************//**
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/**********************************************************************//**
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* Disable specific CPU interrupt.
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* Disable specific CPU interrupt.
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*
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
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if ((irq_sel != CSR_MIE_MSIE) && (irq_sel != CSR_MIE_MTIE) && (irq_sel != CSR_MIE_MEIE) &&
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(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
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(irq_sel != CSR_MIE_FIRQ0E) && (irq_sel != CSR_MIE_FIRQ1E) && (irq_sel != CSR_MIE_FIRQ2E) && (irq_sel != CSR_MIE_FIRQ3E)) {
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return 1;
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return 1;
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}
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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| Line 252... |
Line 252... |
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asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can now use ra as general purpose register in here
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asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can now use ra as general purpose register in here
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"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits
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"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits
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"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode
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"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode
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"mret \n\t" // return and switch to user mode
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"mret \n\t" // return and switch to user mode
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: : [input_imm] "i" ((1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L)));
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: : [input_imm] "i" ((1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L)));
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Atomic compare-and-swap operation (for implemeneting semaphores and mutexes).
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* Atomic compare-and-swap operation (for implemeneting semaphores and mutexes).
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Line 296... |
#endif
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#endif
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Physical memory protection (PMP): Get number of available regions.
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*
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* @warning This function overrides all available PMPCFG* CSRs.
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* @warning This function requires the PMP CPU extension.
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*
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* @return Returns number of available PMP regions.
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**************************************************************************/
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uint32_t neorv32_cpu_pmp_get_num_regions(void) {
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// try setting R bit in all PMPCFG CSRs
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG1, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG2, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG3, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG4, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG5, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG6, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG7, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG8, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG9, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG10, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG11, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG12, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG13, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG14, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG15, 0x01010101);
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// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
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union {
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uint32_t uint32;
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uint8_t uint8[sizeof(uint32_t)/sizeof(uint8_t)];
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} cnt;
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cnt.uint32 = 0;
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG0);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG1);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG2);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG3);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG4);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG5);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG6);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG7);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG8);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG9);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG10);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG11);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG12);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG13);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG14);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG15);
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// sum up bytes
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uint32_t num_regions = 0;
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num_regions += (uint32_t)cnt.uint8[0];
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num_regions += (uint32_t)cnt.uint8[1];
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num_regions += (uint32_t)cnt.uint8[2];
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num_regions += (uint32_t)cnt.uint8[3];
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return num_regions;
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}
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/**********************************************************************//**
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* Physical memory protection (PMP): Get minimal region size (granularity).
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* Physical memory protection (PMP): Get minimal region size (granularity).
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*
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*
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* @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs.
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* @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs.
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*
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* @warning This function requires the PMP CPU extension.
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* @warning This function requires the PMP CPU extension.
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*
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*
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* @return Returns minimal region size in bytes; Returns 0 on failure.
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* @return Returns minimal region size in bytes.
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**************************************************************************/
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**************************************************************************/
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uint32_t neorv32_cpu_pmp_get_granularity(void) {
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uint32_t neorv32_cpu_pmp_get_granularity(void) {
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if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) == 0) {
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return 0; // PMP not implemented
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}
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// check min granulartiy
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// check min granulartiy
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uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
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uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
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tmp &= 0xffffff00; // disable entry 0
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tmp &= 0xffffff00; // disable entry 0
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neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
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neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
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neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
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neorv32_cpu_csr_write(CSR_PMPADDR0, 0xffffffff);
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Line 394... |
* Physical memory protection (PMP): Configure region.
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* Physical memory protection (PMP): Configure region.
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*
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*
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* @note Using NAPOT mode - page base address has to be naturally aligned.
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* @note Using NAPOT mode - page base address has to be naturally aligned.
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*
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*
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* @warning This function requires the PMP CPU extension.
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* @warning This function requires the PMP CPU extension.
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* @warning Only use available PMP regions. Check before using neorv32_cpu_pmp_get_regions(void).
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*
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*
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* @param[in] index Region number (index, 0..max_regions-1).
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* @param[in] index Region number (index, 0..PMP_NUM_REGIONS-1).
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* @param[in] base Region base address (has to be naturally aligned!).
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* @param[in] base Region base address (has to be naturally aligned!).
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* @param[in] size Region size, has to be a power of 2 (min 8 bytes or according to HW's PMP.granularity configuration).
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* @param[in] size Region size, has to be a power of 2 (min 8 bytes or according to HW's PMP.granularity configuration).
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* @param[in] config Region configuration (attributes) byte (for PMPCFGx).
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* @param[in] config Region configuration (attributes) byte (for PMPCFGx).
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* @return Returns 0 on success, 1 on failure.
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* @return Returns 0 on success, 1 on failure.
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config) {
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int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config) {
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if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) == 0) {
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return 1; // PMP not implemented
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}
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if (size < 8) {
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if (size < 8) {
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return 1; // minimal region size is 8 bytes
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return 1; // minimal region size is 8 bytes
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}
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}
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if ((size & (size - 1)) != 0) {
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if ((size & (size - 1)) != 0) {
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| Line 364... |
Line 419... |
uint32_t config_int = ((uint32_t)config) << ((index%4)*8);
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uint32_t config_int = ((uint32_t)config) << ((index%4)*8);
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uint32_t config_mask = ((uint32_t)0xFF) << ((index%4)*8);
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uint32_t config_mask = ((uint32_t)0xFF) << ((index%4)*8);
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config_mask = ~config_mask;
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config_mask = ~config_mask;
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// clear old configuration
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// clear old configuration
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if (index < 3) {
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switch(index & 15) {
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tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
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case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, neorv32_cpu_csr_read(CSR_PMPCFG0) & config_mask); break;
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tmp &= config_mask; // clear old config
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case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, neorv32_cpu_csr_read(CSR_PMPCFG1) & config_mask); break;
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neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
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case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, neorv32_cpu_csr_read(CSR_PMPCFG2) & config_mask); break;
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}
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case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, neorv32_cpu_csr_read(CSR_PMPCFG3) & config_mask); break;
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else {
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case 4: neorv32_cpu_csr_write(CSR_PMPCFG4, neorv32_cpu_csr_read(CSR_PMPCFG4) & config_mask); break;
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tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);
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case 5: neorv32_cpu_csr_write(CSR_PMPCFG5, neorv32_cpu_csr_read(CSR_PMPCFG5) & config_mask); break;
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tmp &= config_mask; // clear old config
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case 6: neorv32_cpu_csr_write(CSR_PMPCFG6, neorv32_cpu_csr_read(CSR_PMPCFG6) & config_mask); break;
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neorv32_cpu_csr_write(CSR_PMPCFG1, tmp);
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case 7: neorv32_cpu_csr_write(CSR_PMPCFG7, neorv32_cpu_csr_read(CSR_PMPCFG7) & config_mask); break;
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case 8: neorv32_cpu_csr_write(CSR_PMPCFG8, neorv32_cpu_csr_read(CSR_PMPCFG8) & config_mask); break;
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case 9: neorv32_cpu_csr_write(CSR_PMPCFG9, neorv32_cpu_csr_read(CSR_PMPCFG9) & config_mask); break;
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case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, neorv32_cpu_csr_read(CSR_PMPCFG10) & config_mask); break;
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case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, neorv32_cpu_csr_read(CSR_PMPCFG11) & config_mask); break;
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case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, neorv32_cpu_csr_read(CSR_PMPCFG12) & config_mask); break;
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case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, neorv32_cpu_csr_read(CSR_PMPCFG13) & config_mask); break;
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case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, neorv32_cpu_csr_read(CSR_PMPCFG14) & config_mask); break;
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case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, neorv32_cpu_csr_read(CSR_PMPCFG15) & config_mask); break;
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default: break;
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}
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}
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// set base address and region size
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// set base address and region size
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uint32_t addr_mask = ~((size - 1) >> 2);
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uint32_t addr_mask = ~((size - 1) >> 2);
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uint32_t size_mask = (size - 1) >> 3;
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uint32_t size_mask = (size - 1) >> 3;
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tmp = base & addr_mask;
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tmp = base & addr_mask;
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tmp = tmp | size_mask;
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tmp = tmp | size_mask;
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switch(index & 7) {
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switch(index & 63) {
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case 0: neorv32_cpu_csr_write(CSR_PMPADDR0, tmp); break;
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case 0: neorv32_cpu_csr_write(CSR_PMPADDR0, tmp); break;
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case 1: neorv32_cpu_csr_write(CSR_PMPADDR1, tmp); break;
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case 1: neorv32_cpu_csr_write(CSR_PMPADDR1, tmp); break;
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case 2: neorv32_cpu_csr_write(CSR_PMPADDR2, tmp); break;
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case 2: neorv32_cpu_csr_write(CSR_PMPADDR2, tmp); break;
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case 3: neorv32_cpu_csr_write(CSR_PMPADDR3, tmp); break;
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case 3: neorv32_cpu_csr_write(CSR_PMPADDR3, tmp); break;
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case 4: neorv32_cpu_csr_write(CSR_PMPADDR4, tmp); break;
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case 4: neorv32_cpu_csr_write(CSR_PMPADDR4, tmp); break;
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case 5: neorv32_cpu_csr_write(CSR_PMPADDR5, tmp); break;
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case 5: neorv32_cpu_csr_write(CSR_PMPADDR5, tmp); break;
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case 6: neorv32_cpu_csr_write(CSR_PMPADDR6, tmp); break;
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case 6: neorv32_cpu_csr_write(CSR_PMPADDR6, tmp); break;
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case 7: neorv32_cpu_csr_write(CSR_PMPADDR7, tmp); break;
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case 7: neorv32_cpu_csr_write(CSR_PMPADDR7, tmp); break;
|
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case 8: neorv32_cpu_csr_write(CSR_PMPADDR8, tmp); break;
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case 9: neorv32_cpu_csr_write(CSR_PMPADDR9, tmp); break;
|
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case 10: neorv32_cpu_csr_write(CSR_PMPADDR10, tmp); break;
|
|
case 11: neorv32_cpu_csr_write(CSR_PMPADDR11, tmp); break;
|
|
case 12: neorv32_cpu_csr_write(CSR_PMPADDR12, tmp); break;
|
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case 13: neorv32_cpu_csr_write(CSR_PMPADDR13, tmp); break;
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case 14: neorv32_cpu_csr_write(CSR_PMPADDR14, tmp); break;
|
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case 15: neorv32_cpu_csr_write(CSR_PMPADDR15, tmp); break;
|
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case 16: neorv32_cpu_csr_write(CSR_PMPADDR16, tmp); break;
|
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case 17: neorv32_cpu_csr_write(CSR_PMPADDR17, tmp); break;
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case 18: neorv32_cpu_csr_write(CSR_PMPADDR18, tmp); break;
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case 19: neorv32_cpu_csr_write(CSR_PMPADDR19, tmp); break;
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case 20: neorv32_cpu_csr_write(CSR_PMPADDR20, tmp); break;
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case 21: neorv32_cpu_csr_write(CSR_PMPADDR21, tmp); break;
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case 22: neorv32_cpu_csr_write(CSR_PMPADDR22, tmp); break;
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case 23: neorv32_cpu_csr_write(CSR_PMPADDR23, tmp); break;
|
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case 24: neorv32_cpu_csr_write(CSR_PMPADDR24, tmp); break;
|
|
case 25: neorv32_cpu_csr_write(CSR_PMPADDR25, tmp); break;
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case 26: neorv32_cpu_csr_write(CSR_PMPADDR26, tmp); break;
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case 27: neorv32_cpu_csr_write(CSR_PMPADDR27, tmp); break;
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case 28: neorv32_cpu_csr_write(CSR_PMPADDR28, tmp); break;
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case 29: neorv32_cpu_csr_write(CSR_PMPADDR29, tmp); break;
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case 30: neorv32_cpu_csr_write(CSR_PMPADDR30, tmp); break;
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case 31: neorv32_cpu_csr_write(CSR_PMPADDR31, tmp); break;
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case 32: neorv32_cpu_csr_write(CSR_PMPADDR32, tmp); break;
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case 33: neorv32_cpu_csr_write(CSR_PMPADDR33, tmp); break;
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case 34: neorv32_cpu_csr_write(CSR_PMPADDR34, tmp); break;
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case 35: neorv32_cpu_csr_write(CSR_PMPADDR35, tmp); break;
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case 36: neorv32_cpu_csr_write(CSR_PMPADDR36, tmp); break;
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case 37: neorv32_cpu_csr_write(CSR_PMPADDR37, tmp); break;
|
|
case 38: neorv32_cpu_csr_write(CSR_PMPADDR38, tmp); break;
|
|
case 39: neorv32_cpu_csr_write(CSR_PMPADDR39, tmp); break;
|
|
case 40: neorv32_cpu_csr_write(CSR_PMPADDR40, tmp); break;
|
|
case 41: neorv32_cpu_csr_write(CSR_PMPADDR41, tmp); break;
|
|
case 42: neorv32_cpu_csr_write(CSR_PMPADDR42, tmp); break;
|
|
case 43: neorv32_cpu_csr_write(CSR_PMPADDR43, tmp); break;
|
|
case 44: neorv32_cpu_csr_write(CSR_PMPADDR44, tmp); break;
|
|
case 45: neorv32_cpu_csr_write(CSR_PMPADDR45, tmp); break;
|
|
case 46: neorv32_cpu_csr_write(CSR_PMPADDR46, tmp); break;
|
|
case 47: neorv32_cpu_csr_write(CSR_PMPADDR47, tmp); break;
|
|
case 48: neorv32_cpu_csr_write(CSR_PMPADDR48, tmp); break;
|
|
case 49: neorv32_cpu_csr_write(CSR_PMPADDR49, tmp); break;
|
|
case 50: neorv32_cpu_csr_write(CSR_PMPADDR50, tmp); break;
|
|
case 51: neorv32_cpu_csr_write(CSR_PMPADDR51, tmp); break;
|
|
case 52: neorv32_cpu_csr_write(CSR_PMPADDR52, tmp); break;
|
|
case 53: neorv32_cpu_csr_write(CSR_PMPADDR53, tmp); break;
|
|
case 54: neorv32_cpu_csr_write(CSR_PMPADDR54, tmp); break;
|
|
case 55: neorv32_cpu_csr_write(CSR_PMPADDR55, tmp); break;
|
|
case 56: neorv32_cpu_csr_write(CSR_PMPADDR56, tmp); break;
|
|
case 57: neorv32_cpu_csr_write(CSR_PMPADDR57, tmp); break;
|
|
case 58: neorv32_cpu_csr_write(CSR_PMPADDR58, tmp); break;
|
|
case 59: neorv32_cpu_csr_write(CSR_PMPADDR59, tmp); break;
|
|
case 60: neorv32_cpu_csr_write(CSR_PMPADDR60, tmp); break;
|
|
case 61: neorv32_cpu_csr_write(CSR_PMPADDR61, tmp); break;
|
|
case 62: neorv32_cpu_csr_write(CSR_PMPADDR62, tmp); break;
|
|
case 63: neorv32_cpu_csr_write(CSR_PMPADDR63, tmp); break;
|
default: break;
|
default: break;
|
}
|
}
|
|
|
// wait for HW to computer PMP-internal stuff (address masks)
|
// wait for HW to compute PMP-internal stuff (address masks)
|
for (tmp=0; tmp<16; tmp++) {
|
for (tmp=0; tmp<16; tmp++) {
|
asm volatile ("nop");
|
asm volatile ("nop");
|
}
|
}
|
|
|
// set new configuration
|
// set new configuration
|
if (index < 3) {
|
switch(index & 15) {
|
tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
|
case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, neorv32_cpu_csr_read(CSR_PMPCFG0) | config_int); break;
|
tmp |= config_int; // set new config
|
case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, neorv32_cpu_csr_read(CSR_PMPCFG1) | config_int); break;
|
neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
|
case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, neorv32_cpu_csr_read(CSR_PMPCFG2) | config_int); break;
|
}
|
case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, neorv32_cpu_csr_read(CSR_PMPCFG3) | config_int); break;
|
else {
|
case 4: neorv32_cpu_csr_write(CSR_PMPCFG4, neorv32_cpu_csr_read(CSR_PMPCFG4) | config_int); break;
|
tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);
|
case 5: neorv32_cpu_csr_write(CSR_PMPCFG5, neorv32_cpu_csr_read(CSR_PMPCFG5) | config_int); break;
|
tmp |= config_int; // set new config
|
case 6: neorv32_cpu_csr_write(CSR_PMPCFG6, neorv32_cpu_csr_read(CSR_PMPCFG6) | config_int); break;
|
neorv32_cpu_csr_write(CSR_PMPCFG1, tmp);
|
case 7: neorv32_cpu_csr_write(CSR_PMPCFG7, neorv32_cpu_csr_read(CSR_PMPCFG7) | config_int); break;
|
|
case 8: neorv32_cpu_csr_write(CSR_PMPCFG8, neorv32_cpu_csr_read(CSR_PMPCFG8) | config_int); break;
|
|
case 9: neorv32_cpu_csr_write(CSR_PMPCFG9, neorv32_cpu_csr_read(CSR_PMPCFG9) | config_int); break;
|
|
case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, neorv32_cpu_csr_read(CSR_PMPCFG10) | config_int); break;
|
|
case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, neorv32_cpu_csr_read(CSR_PMPCFG11) | config_int); break;
|
|
case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, neorv32_cpu_csr_read(CSR_PMPCFG12) | config_int); break;
|
|
case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, neorv32_cpu_csr_read(CSR_PMPCFG13) | config_int); break;
|
|
case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, neorv32_cpu_csr_read(CSR_PMPCFG14) | config_int); break;
|
|
case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, neorv32_cpu_csr_read(CSR_PMPCFG15) | config_int); break;
|
|
default: break;
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
|
/**********************************************************************//**
|
|
* Hardware performance monitors (HPM): Get number of available HPM counters.
|
|
*
|
|
* @warning This function overrides all available mhpmcounter* CSRs.
|
|
*
|
|
* @return Returns number of available HPM counters (..29).
|
|
**************************************************************************/
|
|
uint32_t neorv32_cpu_hpm_get_counters(void) {
|
|
|
|
// try setting all mhpmcounter* CSRs to 1
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER15, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER16, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER17, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER18, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER19, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER20, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER21, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER22, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER23, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER24, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER25, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER26, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER27, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER28, 1);
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER29, 1);
|
|
|
|
// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
|
|
uint32_t num_hpm_cnts = 0;
|
|
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER4);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER5);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER6);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER7);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER8);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER9);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER10);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER11);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER12);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER13);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER14);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER15);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER16);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER17);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER18);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER19);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER20);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER21);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER22);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER23);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER24);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER25);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER26);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER27);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER28);
|
|
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER29);
|
|
|
|
return num_hpm_cnts;
|
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
