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#include "neorv32.h"
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#include "neorv32.h"
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#include "neorv32_cpu.h"
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#include "neorv32_cpu.h"
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/**********************************************************************//**
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* >Private< helper functions.
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**************************************************************************/
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static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index);
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static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data);
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/**********************************************************************//**
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/**********************************************************************//**
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* Enable specific CPU interrupt.
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* Enable specific CPU interrupt.
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*
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*
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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*
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*
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return 1;
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return 1;
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}
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}
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return 0;
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return 0;
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#else
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#else
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return 1; // A extension not implemented -Y always fail
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return 1; // A extension not implemented - function always fails
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#endif
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#endif
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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*
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*
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* @return Returns number of available PMP regions.
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* @return Returns number of available PMP regions.
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**************************************************************************/
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**************************************************************************/
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uint32_t neorv32_cpu_pmp_get_num_regions(void) {
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uint32_t neorv32_cpu_pmp_get_num_regions(void) {
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uint32_t i = 0;
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// try setting R bit in all PMPCFG CSRs
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// try setting R bit in all PMPCFG CSRs
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neorv32_cpu_csr_write(CSR_PMPCFG0, 0x01010101);
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const uint32_t tmp = 0x01010101;
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neorv32_cpu_csr_write(CSR_PMPCFG1, 0x01010101);
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for (i=0; i<16; i++) {
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neorv32_cpu_csr_write(CSR_PMPCFG2, 0x01010101);
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__neorv32_cpu_pmp_cfg_write(i, tmp);
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neorv32_cpu_csr_write(CSR_PMPCFG3, 0x01010101);
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}
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neorv32_cpu_csr_write(CSR_PMPCFG4, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG5, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG6, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG7, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG8, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG9, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG10, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG11, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG12, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG13, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG14, 0x01010101);
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neorv32_cpu_csr_write(CSR_PMPCFG15, 0x01010101);
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// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
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// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
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union {
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union {
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uint32_t uint32;
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uint32_t uint32;
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uint8_t uint8[sizeof(uint32_t)/sizeof(uint8_t)];
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uint8_t uint8[sizeof(uint32_t)/sizeof(uint8_t)];
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} cnt;
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} cnt;
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cnt.uint32 = 0;
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cnt.uint32 = 0;
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG0);
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for (i=0; i<16; i++) {
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG1);
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cnt.uint32 += __neorv32_cpu_pmp_cfg_read(i);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG2);
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}
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG3);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG4);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG5);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG6);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG7);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG8);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG9);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG10);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG11);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG12);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG13);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG14);
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cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG15);
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// sum up bytes
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// sum up bytes
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uint32_t num_regions = 0;
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uint32_t num_regions = 0;
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num_regions += (uint32_t)cnt.uint8[0];
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num_regions += (uint32_t)cnt.uint8[0];
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num_regions += (uint32_t)cnt.uint8[1];
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num_regions += (uint32_t)cnt.uint8[1];
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Line 397... |
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if ((size & (size - 1)) != 0) {
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if ((size & (size - 1)) != 0) {
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return 1; // region size is not a power of two
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return 1; // region size is not a power of two
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}
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}
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// pmpcfg register index
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uint32_t pmpcfg_index = index >> 4; // 4 entries per pmpcfg csr
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// setup configuration
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// setup configuration
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uint32_t tmp;
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uint32_t tmp;
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uint32_t config_int = ((uint32_t)config) << ((index%4)*8);
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uint32_t config_int = ((uint32_t)config) << ((index%4)*8);
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uint32_t config_mask = ((uint32_t)0xFF) << ((index%4)*8);
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uint32_t config_mask = ((uint32_t)0xFF) << ((index%4)*8);
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config_mask = ~config_mask;
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config_mask = ~config_mask;
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// clear old configuration
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// clear old configuration
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switch(index & 15) {
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__neorv32_cpu_pmp_cfg_write(pmpcfg_index, __neorv32_cpu_pmp_cfg_read(pmpcfg_index) & config_mask);
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case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, neorv32_cpu_csr_read(CSR_PMPCFG0) & config_mask); break;
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case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, neorv32_cpu_csr_read(CSR_PMPCFG1) & config_mask); break;
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case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, neorv32_cpu_csr_read(CSR_PMPCFG2) & config_mask); break;
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case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, neorv32_cpu_csr_read(CSR_PMPCFG3) & config_mask); break;
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case 4: neorv32_cpu_csr_write(CSR_PMPCFG4, neorv32_cpu_csr_read(CSR_PMPCFG4) & config_mask); break;
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case 5: neorv32_cpu_csr_write(CSR_PMPCFG5, neorv32_cpu_csr_read(CSR_PMPCFG5) & config_mask); break;
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case 6: neorv32_cpu_csr_write(CSR_PMPCFG6, neorv32_cpu_csr_read(CSR_PMPCFG6) & config_mask); break;
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case 7: neorv32_cpu_csr_write(CSR_PMPCFG7, neorv32_cpu_csr_read(CSR_PMPCFG7) & config_mask); break;
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case 8: neorv32_cpu_csr_write(CSR_PMPCFG8, neorv32_cpu_csr_read(CSR_PMPCFG8) & config_mask); break;
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case 9: neorv32_cpu_csr_write(CSR_PMPCFG9, neorv32_cpu_csr_read(CSR_PMPCFG9) & config_mask); break;
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case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, neorv32_cpu_csr_read(CSR_PMPCFG10) & config_mask); break;
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case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, neorv32_cpu_csr_read(CSR_PMPCFG11) & config_mask); break;
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case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, neorv32_cpu_csr_read(CSR_PMPCFG12) & config_mask); break;
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case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, neorv32_cpu_csr_read(CSR_PMPCFG13) & config_mask); break;
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case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, neorv32_cpu_csr_read(CSR_PMPCFG14) & config_mask); break;
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case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, neorv32_cpu_csr_read(CSR_PMPCFG15) & config_mask); break;
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default: break;
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}
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// set base address and region size
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// set base address and region size
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uint32_t addr_mask = ~((size - 1) >> 2);
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uint32_t addr_mask = ~((size - 1) >> 2);
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uint32_t size_mask = (size - 1) >> 3;
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uint32_t size_mask = (size - 1) >> 3;
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Line 491... |
for (tmp=0; tmp<16; tmp++) {
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for (tmp=0; tmp<16; tmp++) {
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asm volatile ("nop");
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asm volatile ("nop");
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}
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}
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// set new configuration
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// set new configuration
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__neorv32_cpu_pmp_cfg_write(pmpcfg_index, __neorv32_cpu_pmp_cfg_read(pmpcfg_index) | config_int);
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return 0;
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}
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/**********************************************************************//**
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* Internal helper function: Read PMP configuration register 0..15
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*
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* @warning This function requires the PMP CPU extension.
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*
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* @param[in] index PMP CFG configuration register ID (0..15).
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* @return PMP CFG read data.
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**************************************************************************/
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static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index) {
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uint32_t tmp = 0;
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switch(index & 15) {
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switch(index & 15) {
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case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, neorv32_cpu_csr_read(CSR_PMPCFG0) | config_int); break;
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case 0: tmp = neorv32_cpu_csr_read(CSR_PMPCFG0); break;
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case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, neorv32_cpu_csr_read(CSR_PMPCFG1) | config_int); break;
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case 1: tmp = neorv32_cpu_csr_read(CSR_PMPCFG1); break;
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case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, neorv32_cpu_csr_read(CSR_PMPCFG2) | config_int); break;
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case 2: tmp = neorv32_cpu_csr_read(CSR_PMPCFG2); break;
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case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, neorv32_cpu_csr_read(CSR_PMPCFG3) | config_int); break;
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case 3: tmp = neorv32_cpu_csr_read(CSR_PMPCFG3); break;
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case 4: neorv32_cpu_csr_write(CSR_PMPCFG4, neorv32_cpu_csr_read(CSR_PMPCFG4) | config_int); break;
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case 4: tmp = neorv32_cpu_csr_read(CSR_PMPCFG4); break;
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case 5: neorv32_cpu_csr_write(CSR_PMPCFG5, neorv32_cpu_csr_read(CSR_PMPCFG5) | config_int); break;
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case 5: tmp = neorv32_cpu_csr_read(CSR_PMPCFG5); break;
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case 6: neorv32_cpu_csr_write(CSR_PMPCFG6, neorv32_cpu_csr_read(CSR_PMPCFG6) | config_int); break;
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case 6: tmp = neorv32_cpu_csr_read(CSR_PMPCFG6); break;
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case 7: neorv32_cpu_csr_write(CSR_PMPCFG7, neorv32_cpu_csr_read(CSR_PMPCFG7) | config_int); break;
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case 7: tmp = neorv32_cpu_csr_read(CSR_PMPCFG7); break;
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case 8: neorv32_cpu_csr_write(CSR_PMPCFG8, neorv32_cpu_csr_read(CSR_PMPCFG8) | config_int); break;
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case 8: tmp = neorv32_cpu_csr_read(CSR_PMPCFG8); break;
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case 9: neorv32_cpu_csr_write(CSR_PMPCFG9, neorv32_cpu_csr_read(CSR_PMPCFG9) | config_int); break;
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case 9: tmp = neorv32_cpu_csr_read(CSR_PMPCFG9); break;
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case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, neorv32_cpu_csr_read(CSR_PMPCFG10) | config_int); break;
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case 10: tmp = neorv32_cpu_csr_read(CSR_PMPCFG10); break;
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case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, neorv32_cpu_csr_read(CSR_PMPCFG11) | config_int); break;
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case 11: tmp = neorv32_cpu_csr_read(CSR_PMPCFG11); break;
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case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, neorv32_cpu_csr_read(CSR_PMPCFG12) | config_int); break;
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case 12: tmp = neorv32_cpu_csr_read(CSR_PMPCFG12); break;
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case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, neorv32_cpu_csr_read(CSR_PMPCFG13) | config_int); break;
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case 13: tmp = neorv32_cpu_csr_read(CSR_PMPCFG13); break;
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case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, neorv32_cpu_csr_read(CSR_PMPCFG14) | config_int); break;
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case 14: tmp = neorv32_cpu_csr_read(CSR_PMPCFG14); break;
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case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, neorv32_cpu_csr_read(CSR_PMPCFG15) | config_int); break;
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case 15: tmp = neorv32_cpu_csr_read(CSR_PMPCFG15); break;
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default: break;
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default: break;
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}
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}
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return 0;
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return tmp;
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}
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/**********************************************************************//**
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* Internal helper function: Write PMP configuration register 0..15
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*
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* @warning This function requires the PMP CPU extension.
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*
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* @param[in] index PMP CFG configuration register ID (0..15).
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* @param[in] data PMP CFG write data.
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**************************************************************************/
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static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data) {
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switch(index & 15) {
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case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, data); break;
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case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, data); break;
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case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, data); break;
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case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, data); break;
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case 4: neorv32_cpu_csr_write(CSR_PMPCFG4, data); break;
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case 5: neorv32_cpu_csr_write(CSR_PMPCFG5, data); break;
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case 6: neorv32_cpu_csr_write(CSR_PMPCFG6, data); break;
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case 7: neorv32_cpu_csr_write(CSR_PMPCFG7, data); break;
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case 8: neorv32_cpu_csr_write(CSR_PMPCFG8, data); break;
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case 9: neorv32_cpu_csr_write(CSR_PMPCFG9, data); break;
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case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, data); break;
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case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, data); break;
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case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, data); break;
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case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, data); break;
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case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, data); break;
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case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, data); break;
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default: break;
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}
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Hardware performance monitors (HPM): Get number of available HPM counters.
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* Hardware performance monitors (HPM): Get number of available HPM counters.
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