| Line 320... |
Line 320... |
: : [input_imm] "i" ((1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L)));
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: : [input_imm] "i" ((1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L)));
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Atomic compare-and-swap operation (for implemeneting semaphores and mutexes).
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*
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* @warning This function requires the A (atomic) CPU extension.
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*
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* @param[in] addr Address of memory location.
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* @param[in] expected Expected value (for comparison).
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* @param[in] desired Desired value (new value).
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* @return Returns 0 on success, 1 on failure.
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**************************************************************************/
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int __attribute__ ((noinline)) neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired) {
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#ifdef __riscv_atomic
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register uint32_t addr_reg = addr;
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register uint32_t des_reg = desired;
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register uint32_t tmp_reg;
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// load original value + reservation (lock)
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asm volatile ("lr.w %[result], (%[input])" : [result] "=r" (tmp_reg) : [input] "r" (addr_reg));
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if (tmp_reg != expected) {
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asm volatile ("lw x0, 0(%[input])" : : [input] "r" (addr_reg)); // clear reservation lock
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return 1;
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}
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// store-conditional
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asm volatile ("sc.w %[result], %[input_i], (%[input_j])" : [result] "=r" (tmp_reg) : [input_i] "r" (des_reg), [input_j] "r" (addr_reg));
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if (tmp_reg) {
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return 1;
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}
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return 0;
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#else
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return 1; // A extension not implemented - function always fails
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#endif
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}
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/**********************************************************************//**
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* Physical memory protection (PMP): Get number of available regions.
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* Physical memory protection (PMP): Get number of available regions.
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*
|
*
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* @warning This function overrides all available PMPCFG* CSRs.
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* @warning This function overrides all available PMPCFG* CSRs.
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* @warning This function requires the PMP CPU extension.
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* @warning This function requires the PMP CPU extension.
|
*
|
*
|
