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Line 44... |
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/**********************************************************************//**
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/**********************************************************************//**
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* Unavailable extensions warning.
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* Unavailable extensions warning.
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**************************************************************************/
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**************************************************************************/
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#if defined __riscv_f || (__riscv_flen == 32)
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#warning Single-precision floating-point extension <F/Zfinx> is WORK-IN-PROGRESS and there is NO NATIVE SUPPORT BY THE COMPILER yet!
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#endif
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#if defined __riscv_d || (__riscv_flen == 64)
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#if defined __riscv_d || (__riscv_flen == 64)
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#error Double-precision floating-point extension <D/Zdinx> is NOT supported!
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#error Double-precision floating-point extension <D/Zdinx> is NOT supported!
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#endif
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#endif
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#if (__riscv_xlen > 32)
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#if (__riscv_xlen > 32)
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#error Only 32-bit <rv32> is supported!
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#error Only 32-bit <rv32> is supported!
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#endif
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#endif
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#ifdef __riscv_b
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#warning Bit-manipulation extension <B> is still experimental (non-ratified) and does not support all <Zb*> subsets yet.
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#endif
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#ifdef __riscv_fdiv
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#ifdef __riscv_fdiv
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#warning Floating-point division instruction <FDIV> is NOT supported yet!
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#warning Floating-point division instruction <FDIV> is NOT supported yet!
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#endif
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#endif
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#ifdef __riscv_fsqrt
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#ifdef __riscv_fsqrt
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Line 263... |
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/**********************************************************************//**
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/**********************************************************************//**
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* Delay function using busy wait.
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* Delay function using busy wait.
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*
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*
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* @note This function uses the time CSRs (from int./ext. MTIME). A simple ASM loop
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* @note This function uses MTIME as time base. A simple ASM loop
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* is used as fall back if system timer is not advancing (no MTIME available).
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* is used as fall back if system timer is not implemented.
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*
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*
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* @warning Delay time might be less precise if M extensions is not available
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* @warning Delay time might be less precise if M extensions is not available
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* (especially if MTIME unit is not available).
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* (especially if MTIME unit is not available).
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*
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*
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* @param[in] time_ms Time in ms to wait (unsigned 32-bit).
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* @param[in] time_ms Time in ms to wait (unsigned 32-bit).
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Line 276... |
void neorv32_cpu_delay_ms(uint32_t time_ms) {
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void neorv32_cpu_delay_ms(uint32_t time_ms) {
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uint32_t clock = NEORV32_SYSINFO.CLK; // clock ticks per second
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uint32_t clock = NEORV32_SYSINFO.CLK; // clock ticks per second
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clock = clock / 1000; // clock ticks per ms
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clock = clock / 1000; // clock ticks per ms
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uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
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register uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms);
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register uint64_t tmp = 0;
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register uint64_t tmp = neorv32_cpu_get_systime();
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// MTIME available?
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if (neorv32_cpu_get_systime() > tmp) { // system time advancing (MTIME available and running)?
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if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_MTIME)) {
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// use MTIME machine timer
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// use MTIME machine timer
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tmp += wait_cycles;
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tmp = neorv32_mtime_get_time() + wait_cycles;
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while(1) {
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while(1) {
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if (neorv32_cpu_get_systime() >= tmp) {
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if (neorv32_mtime_get_time() >= tmp) {
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break;
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break;
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}
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}
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}
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}
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}
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}
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else {
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else {
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// use ASM loop
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// use ASM loop
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// warning! not really precise (especially if M extensions is not available)!
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// warning! not really precise (especially if M extensions is not available)!
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const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop
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const uint32_t loop_cycles_c = 16; // clock cycles per iteration of the ASM loop
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uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c);
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register uint32_t iterations = (uint32_t)(wait_cycles / loop_cycles_c); // M (div) extension would be nice here!
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asm volatile (" .balign 4 \n" // make sure this is 32-bit aligned
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asm volatile (" .balign 4 \n" // make sure this is 32-bit aligned
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" __neorv32_cpu_delay_ms_start: \n"
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" __neorv32_cpu_delay_ms_start: \n"
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" beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (not taken)
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" beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (not taken)
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" beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (never taken)
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" beq %[cnt_r], zero, __neorv32_cpu_delay_ms_end \n" // 3 cycles (never taken)
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Line 338... |
* @return Returns number of available PMP regions.
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* @return Returns number of available PMP regions.
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**************************************************************************/
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**************************************************************************/
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uint32_t neorv32_cpu_pmp_get_num_regions(void) {
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uint32_t neorv32_cpu_pmp_get_num_regions(void) {
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// PMP implemented at all?
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// PMP implemented at all?
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if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_PMP)) == 0) {
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if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_PMP)) == 0) {
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return 0;
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return 0;
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}
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}
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uint32_t i = 0;
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uint32_t i = 0;
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Line 603... |
* @return Returns number of available HPM counters (0..29).
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* @return Returns number of available HPM counters (0..29).
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**************************************************************************/
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**************************************************************************/
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uint32_t neorv32_cpu_hpm_get_counters(void) {
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uint32_t neorv32_cpu_hpm_get_counters(void) {
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// HPMs implemented at all?
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// HPMs implemented at all?
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if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_ZIHPM)) == 0) {
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if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZIHPM)) == 0) {
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return 0;
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return 0;
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}
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}
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// inhibit all HPM counters
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// inhibit all HPM counters
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uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
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uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
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Line 686... |
* @return Size of HPM counter bits (1-64, 0 if not implemented at all).
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* @return Size of HPM counter bits (1-64, 0 if not implemented at all).
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**************************************************************************/
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**************************************************************************/
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uint32_t neorv32_cpu_hpm_get_size(void) {
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uint32_t neorv32_cpu_hpm_get_size(void) {
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// HPMs implemented at all?
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// HPMs implemented at all?
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if ((NEORV32_SYSINFO.CPU & (1<<SYSINFO_CPU_ZIHPM)) == 0) {
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if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZIHPM)) == 0) {
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return 0;
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return 0;
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}
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}
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// inhibt auto-update
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// inhibt auto-update
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asm volatile ("csrwi %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_HPM3));
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asm volatile ("csrwi %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_HPM3));
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