| Line 50... |
Line 50... |
*
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*
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* @return 0 if PWM was not synthesized, 1 if PWM is available.
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* @return 0 if PWM was not synthesized, 1 if PWM is available.
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**************************************************************************/
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**************************************************************************/
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int neorv32_pwm_available(void) {
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int neorv32_pwm_available(void) {
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|
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if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_PWM)) {
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if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_PWM)) {
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return 1;
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return 1;
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}
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}
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else {
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else {
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return 0;
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return 0;
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}
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}
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Enable and configure pulse width modulation controller. The PWM control register bits are listed in #NEORV32_PWM_CT_enum.
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* Enable and configure pulse width modulation controller. The PWM control register bits are listed in #NEORV32_PWM_CTRL_enum.
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*
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*
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* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
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* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
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**************************************************************************/
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**************************************************************************/
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void neorv32_pwm_setup(uint8_t prsc) {
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void neorv32_pwm_setup(uint8_t prsc) {
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|
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PWM_CT = 0; // reset
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NEORV32_PWM.CTRL = 0; // reset
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|
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uint32_t ct_enable = 1;
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uint32_t ct_enable = 1;
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ct_enable = ct_enable << PWM_CT_EN;
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ct_enable = ct_enable << PWM_CTRL_EN;
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|
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uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
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uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
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ct_prsc = ct_prsc << PWM_CT_PRSC0;
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ct_prsc = ct_prsc << PWM_CTRL_PRSC0;
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PWM_CT = ct_enable | ct_prsc;
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NEORV32_PWM.CTRL = ct_enable | ct_prsc;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Disable pulse width modulation controller.
|
* Disable pulse width modulation controller.
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**************************************************************************/
|
**************************************************************************/
|
void neorv32_pwm_disable(void) {
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void neorv32_pwm_disable(void) {
|
|
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PWM_CT &= ~((uint32_t)(1 << PWM_CT_EN));
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NEORV32_PWM.CTRL &= ~((uint32_t)(1 << PWM_CTRL_EN));
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}
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}
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|
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|
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/**********************************************************************//**
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/**********************************************************************//**
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* Enable pulse width modulation controller.
|
* Enable pulse width modulation controller.
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**************************************************************************/
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**************************************************************************/
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void neorv32_pwm_enable(void) {
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void neorv32_pwm_enable(void) {
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|
|
PWM_CT |= ((uint32_t)(1 << PWM_CT_EN));
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NEORV32_PWM.CTRL |= ((uint32_t)(1 << PWM_CTRL_EN));
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}
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}
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|
|
|
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/**********************************************************************//**
|
/**********************************************************************//**
|
* Get number of implemented channels.
|
* Get number of implemented channels.
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| Line 130... |
Line 130... |
|
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if (channel > 59) {
|
if (channel > 59) {
|
return; // out-of-range
|
return; // out-of-range
|
}
|
}
|
|
|
// compute duty-cycle offset
|
|
uint32_t reg_offset = (uint32_t)(channel / 4);
|
|
uint8_t byte_offset = channel % 4;
|
|
|
|
// read-modify-write
|
// read-modify-write
|
uint32_t duty_mask = 0xff;
|
uint32_t duty_mask = 0xff;
|
uint32_t duty_new = (uint32_t)duty;
|
uint32_t duty_new = (uint32_t)duty;
|
|
|
duty_mask = duty_mask << (byte_offset * 8);
|
duty_mask = duty_mask << ((channel % 4) * 8);
|
duty_new = duty_new << (byte_offset * 8);
|
duty_new = duty_new << ((channel % 4) * 8);
|
|
|
uint32_t duty_cycle = (*(IO_REG32 (&PWM_DUTY0 + reg_offset)));
|
uint32_t duty_cycle = NEORV32_PWM.DUTY[channel/4];
|
|
|
duty_cycle &= ~duty_mask; // clear previous duty cycle
|
duty_cycle &= ~duty_mask; // clear previous duty cycle
|
duty_cycle |= duty_new; // set new duty cycle
|
duty_cycle |= duty_new; // set new duty cycle
|
|
|
(*(IO_REG32 (&PWM_DUTY0 + reg_offset))) = duty_cycle;
|
NEORV32_PWM.DUTY[channel/4] = duty_cycle;
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Get duty cycle from channel.
|
* Get duty cycle from channel.
|
| Line 162... |
Line 158... |
|
|
if (channel > 59) {
|
if (channel > 59) {
|
return 0; // out-of-range
|
return 0; // out-of-range
|
}
|
}
|
|
|
// compute duty-cycle offset
|
uint32_t reg_data = NEORV32_PWM.DUTY[channel/4] >> (((channel % 4) * 8));
|
uint32_t reg_offset = (uint32_t)(channel / 4);
|
|
uint8_t byte_offset = channel % 4;
|
|
|
|
// read
|
|
uint32_t tmp = (*(IO_REG32 (&PWM_DUTY0 + reg_offset)));
|
|
tmp = tmp >> ((byte_offset * 8));
|
|
|
|
return (uint8_t)tmp;
|
return (uint8_t)reg_data;
|
}
|
}
|
|
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No newline at end of file
|
No newline at end of file
|
