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Line 60... |
* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
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* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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**************************************************************************/
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**************************************************************************/
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void neorv32_rte_setup(void) {
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void neorv32_rte_setup(void) {
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// check if CSR system is available at all
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if (neorv32_cpu_csr_read(CSR_MISA) == 0) {
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neorv32_uart_printf("<RTE> WARNING! CPU CSR system not available! </RTE>");
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}
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// configure trap handler base address
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// configure trap handler base address
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uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
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uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
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neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
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neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
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// install debug handler for all sources
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// install debug handler for all sources
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case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break;
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case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call"); break;
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case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break;
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case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break;
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case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break;
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case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break;
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case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break;
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case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break;
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case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt 0 (WDT)"); break;
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case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt 0"); break;
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case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt 1 (GPIO)"); break;
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case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt 1"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt 2 (UART)"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt 2"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt 3 (SPI/TWI)"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt 3"); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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}
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}
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// address
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// address
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_inst;
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register uint32_t trap_inst;
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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if ((trap_cause & 0x80000000) == 0) {
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if ((trap_cause & 0x80000000) == 0) { // is exception?
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if ((trap_inst & 3) == 3) {
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if ((trap_inst & 3) == 3) { // is uncompressed instruction?
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trap_addr -= 4;
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trap_addr -= 4;
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}
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}
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else {
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else {
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trap_addr -= 2;
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trap_addr -= 2;
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}
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}
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