| Line 225... |
Line 225... |
// address
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// address
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_inst;
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register uint32_t trap_inst;
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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// modify return address only if exception (NOT for interrupts)
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if ((trap_cause & 0x80000000) == 0) { // is exception?
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if ((trap_cause & 0x80000000) == 0) { // is exception?
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if ((trap_inst & 3) == 3) { // is uncompressed instruction?
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if ((trap_inst & 3) == 3) { // is uncompressed instruction?
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trap_addr -= 4;
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trap_addr -= 4;
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}
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}
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else {
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else {
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| Line 246... |
Line 247... |
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uint32_t tmp;
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uint32_t tmp;
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int i;
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int i;
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char c;
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char c;
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neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");
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neorv32_uart_printf("\n\n<< Hardware Configuration Overview >>\n");
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// CPU configuration
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// CPU configuration
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neorv32_uart_printf("\n-- Central Processing Unit --\n");
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neorv32_uart_printf("\n-- Central Processing Unit --\n");
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// ID
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// ID
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| Line 258... |
Line 259... |
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neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
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neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
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tmp = neorv32_cpu_csr_read(CSR_MARCHID);
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tmp = neorv32_cpu_csr_read(CSR_MARCHID);
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neorv32_uart_printf("Architecture ID: 0x%x", tmp);
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neorv32_uart_printf("Architecture ID: 0x%x", tmp);
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if (tmp == NEORV32_ARCHID) {
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neorv32_uart_printf(" (NEORV32)");
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}
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// HW version
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// HW version
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neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
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neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
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neorv32_rte_print_hw_version();
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neorv32_rte_print_hw_version();
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neorv32_uart_printf(")\n");
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neorv32_uart_printf(")\n");
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