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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_rte.c] - Diff between revs 30 and 32

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Rev 30 Rev 32
Line 225... Line 225...
  // address
  // address
  register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
  register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
  register uint32_t trap_inst;
  register uint32_t trap_inst;
  asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
  asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
 
 
 
  // modify return address only if exception (NOT for interrupts)
  if ((trap_cause & 0x80000000) == 0) { // is exception?
  if ((trap_cause & 0x80000000) == 0) { // is exception?
    if ((trap_inst & 3) == 3) { // is uncompressed instruction?
    if ((trap_inst & 3) == 3) { // is uncompressed instruction?
      trap_addr -= 4;
      trap_addr -= 4;
    }
    }
    else {
    else {
Line 246... Line 247...
 
 
  uint32_t tmp;
  uint32_t tmp;
  int i;
  int i;
  char c;
  char c;
 
 
  neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");
  neorv32_uart_printf("\n\n<< Hardware Configuration Overview >>\n");
 
 
  // CPU configuration
  // CPU configuration
  neorv32_uart_printf("\n-- Central Processing Unit --\n");
  neorv32_uart_printf("\n-- Central Processing Unit --\n");
 
 
  // ID
  // ID
Line 258... Line 259...
 
 
  neorv32_uart_printf("Vendor ID:         0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
  neorv32_uart_printf("Vendor ID:         0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
 
 
  tmp = neorv32_cpu_csr_read(CSR_MARCHID);
  tmp = neorv32_cpu_csr_read(CSR_MARCHID);
  neorv32_uart_printf("Architecture ID:   0x%x", tmp);
  neorv32_uart_printf("Architecture ID:   0x%x", tmp);
 
  if (tmp == NEORV32_ARCHID) {
 
    neorv32_uart_printf(" (NEORV32)");
 
  }
 
 
  // HW version
  // HW version
  neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
  neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
  neorv32_rte_print_hw_version();
  neorv32_rte_print_hw_version();
  neorv32_uart_printf(")\n");
  neorv32_uart_printf(")\n");

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