| Line 49... |
Line 49... |
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// private functions
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// private functions
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static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused));
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static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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static void __neorv32_rte_print_hex_word(uint32_t num);
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/**********************************************************************//**
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/**********************************************************************//**
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* Setup NEORV32 runtime environment.
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* Setup NEORV32 runtime environment.
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*
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*
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Line 63... |
**************************************************************************/
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**************************************************************************/
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void neorv32_rte_setup(void) {
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void neorv32_rte_setup(void) {
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// check if CSR system is available at all
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// check if CSR system is available at all
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if (neorv32_cpu_csr_read(CSR_MISA) == 0) {
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if (neorv32_cpu_csr_read(CSR_MISA) == 0) {
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neorv32_uart_printf("<RTE> WARNING! CPU CSR system not available! </RTE>");
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neorv32_uart_print("<RTE> WARNING! CPU CSR system not available! </RTE>");
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}
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}
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// configure trap handler base address
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// configure trap handler base address
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uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
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uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
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neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
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neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
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Line 136... |
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/**********************************************************************//**
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/**********************************************************************//**
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* This is the core of the NEORV32 RTE.
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* This is the core of the NEORV32 RTE.
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*
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*
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* @note This function must no be explicitly used by the user.
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* @note This function must no be explicitly used by the user.
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* @note The RTE core uses mscratch CSR to store the trap-causing mepc for further (user-defined) processing.
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*
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* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute!
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* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute!
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**************************************************************************/
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**************************************************************************/
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static void __attribute__((__interrupt__)) __attribute__((aligned(16))) __neorv32_rte_core(void) {
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static void __attribute__((__interrupt__)) __attribute__((aligned(16))) __neorv32_rte_core(void) {
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register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
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neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later
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register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
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// compute return address
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// compute return address
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if ((rte_mcause & 0x80000000) == 0) { // modify pc only if exception
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if ((rte_mcause & 0x80000000) == 0) { // modify pc only if exception
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* @note This function is used by neorv32_rte_exception_uninstall(void) only.
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* @note This function is used by neorv32_rte_exception_uninstall(void) only.
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**************************************************************************/
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**************************************************************************/
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static void __neorv32_rte_debug_exc_handler(void) {
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static void __neorv32_rte_debug_exc_handler(void) {
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// intro
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// intro
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neorv32_uart_printf("<RTE> ");
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neorv32_uart_print("<RTE> ");
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// cause
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// cause
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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switch (trap_cause) {
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switch (trap_cause) {
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case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break;
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case TRAP_CODE_I_MISALIGNED: neorv32_uart_print("Instruction address misaligned"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart_print("Instruction access fault"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart_print("Illegal instruction"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart_print("Breakpoint"); break;
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case TRAP_CODE_L_MISALIGNED: neorv32_uart_printf("Load address misaligned"); break;
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case TRAP_CODE_L_MISALIGNED: neorv32_uart_print("Load address misaligned"); break;
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case TRAP_CODE_L_ACCESS: neorv32_uart_printf("Load access fault"); break;
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case TRAP_CODE_L_ACCESS: neorv32_uart_print("Load access fault"); break;
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case TRAP_CODE_S_MISALIGNED: neorv32_uart_printf("Store address misaligned"); break;
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case TRAP_CODE_S_MISALIGNED: neorv32_uart_print("Store address misaligned"); break;
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case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break;
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case TRAP_CODE_S_ACCESS: neorv32_uart_print("Store access fault"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart_print("Environment call"); break;
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case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break;
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case TRAP_CODE_MSI: neorv32_uart_print("Machine software interrupt"); break;
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case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break;
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case TRAP_CODE_MTI: neorv32_uart_print("Machine timer interrupt"); break;
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case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break;
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case TRAP_CODE_MEI: neorv32_uart_print("Machine external interrupt"); break;
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case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt 0"); break;
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case TRAP_CODE_FIRQ_0: neorv32_uart_print("Fast interrupt 0"); break;
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case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt 1"); break;
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case TRAP_CODE_FIRQ_1: neorv32_uart_print("Fast interrupt 1"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt 2"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_print("Fast interrupt 2"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt 3"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_print("Fast interrupt 3"); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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default: neorv32_uart_print("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break;
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}
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}
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// address
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// instruction address
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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neorv32_uart_print(" @ ");
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register uint32_t trap_inst;
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__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MSCRATCH)); // rte core stores actual mepc to mscratch
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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// additional info
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// modify return address only if exception (NOT for interrupts)
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neorv32_uart_print(", MTVAL=");
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if ((trap_cause & 0x80000000) == 0) { // is exception?
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__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MTVAL));
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if ((trap_inst & 3) == 3) { // is uncompressed instruction?
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neorv32_uart_print(" </RTE>");
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trap_addr -= 4;
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}
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else {
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trap_addr -= 2;
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}
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}
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neorv32_uart_printf(" @ 0x%x, MTVAL=0x%x </RTE>", trap_addr, neorv32_cpu_csr_read(CSR_MTVAL));
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* NEORV32 runtime environment: Print hardware configuration information via UART
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* NEORV32 runtime environment: Print hardware configuration information via UART
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Line 295... |
}
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}
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}
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}
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// Z* CPU extensions (from custom CSR "mzext")
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// Z* CPU extensions (from custom CSR "mzext")
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tmp = neorv32_cpu_csr_read(CSR_MZEXT);
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tmp = neorv32_cpu_csr_read(CSR_MZEXT);
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if (tmp & (1<<0)) {
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if (tmp & (1<<CPU_MZEXT_ZICSR)) {
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neorv32_uart_printf("Zicsr ");
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neorv32_uart_printf("Zicsr ");
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}
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}
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if (tmp & (1<<1)) {
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if (tmp & (1<<CPU_MZEXT_ZIFENCEI)) {
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neorv32_uart_printf("Zifencei ");
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neorv32_uart_printf("Zifencei ");
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}
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}
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if (tmp & (1<<CPU_MZEXT_PMP)) {
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neorv32_uart_printf("PMP ");
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}
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// Misc
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// Misc
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neorv32_uart_printf("\n\n\n-- Processor --\n");
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neorv32_uart_printf("\n\n\n-- Processor --\n");
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neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
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neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
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Line 376... |
* @param[in] state Print TRUE when !=0, print FALSE when 0
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* @param[in] state Print TRUE when !=0, print FALSE when 0
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**************************************************************************/
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**************************************************************************/
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static void __neorv32_rte_print_true_false(int state) {
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static void __neorv32_rte_print_true_false(int state) {
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if (state) {
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if (state) {
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neorv32_uart_printf("True\n");
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neorv32_uart_print("True\n");
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}
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}
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else {
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else {
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neorv32_uart_printf("False\n");
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neorv32_uart_print("False\n");
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}
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Private function to print 32-bit number
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* as 8-digit hexadecimal value (with "0x" suffix).
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*
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* @param[in] num Number to print as hexadecimal.
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**************************************************************************/
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void __neorv32_rte_print_hex_word(uint32_t num) {
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static const char hex_symbols[16] = "0123456789ABCDEF";
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neorv32_uart_print("0x");
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int i;
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for (i=0; i<8; i++) {
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uint32_t index = (num >> (28 - 4*i)) & 0xF;
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neorv32_uart_putc(hex_symbols[index]);
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}
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}
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* NEORV32 runtime environment: Function to show the processor version in human-readable format.
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* NEORV32 runtime environment: Function to show the processor version in human-readable format.
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**************************************************************************/
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**************************************************************************/
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void neorv32_rte_print_hw_version(void) {
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void neorv32_rte_print_hw_version(void) {
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uint32_t i;
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uint32_t i;
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char tmp, cnt;
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char tmp, cnt;
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uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID);
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for (i=0; i<4; i++) {
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for (i=0; i<4; i++) {
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tmp = (char)(version >> (24 - 8*i));
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tmp = (char)(neorv32_cpu_csr_read(CSR_MIMPID) >> (24 - 8*i));
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// serial division
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// serial division
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cnt = 0;
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cnt = 0;
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while (tmp >= 10) {
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while (tmp >= 10) {
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tmp = tmp - 10;
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tmp = tmp - 10;
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