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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_rte.c] - Diff between revs 43 and 44

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Rev 43 Rev 44
Line 312... Line 312...
    neorv32_uart_printf("Zicsr ");
    neorv32_uart_printf("Zicsr ");
  }
  }
  if (tmp & (1<<CSR_MZEXT_ZIFENCEI)) {
  if (tmp & (1<<CSR_MZEXT_ZIFENCEI)) {
    neorv32_uart_printf("Zifencei ");
    neorv32_uart_printf("Zifencei ");
  }
  }
 
  if (tmp & (1<<CSR_MZEXT_ZBB)) {
 
    neorv32_uart_printf("Zbb ");
 
  }
 
 
  // check physical memory protection
  // check physical memory protection
  neorv32_uart_printf("\nPMP:               ");
  neorv32_uart_printf("\nPMP:               ");
  uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
  uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
  if (pmp_num_regions != 0)  {
  if (pmp_num_regions != 0)  {
Line 595... Line 598...
  "\n"
  "\n"
  );
  );
}
}
 
 
 
 
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/**********************************************************************//**
 
 * NEORV32 runtime environment: Get MISA CSR value according to *compiler/toolchain configuration*.
 
 *
 
 * @return MISA content according to compiler configuration.
 
 **************************************************************************/
 
uint32_t neorv32_rte_get_compiler_isa(void) {
 
 
 
  uint32_t misa_cc = 0;
 
 
 
#ifdef __riscv_atomic
 
  misa_cc |= 1 << CSR_MISA_A_EXT;
 
#endif
 
 
 
#ifdef __riscv_compressed
 
  misa_cc |= 1 << CSR_MISA_C_EXT;
 
#endif
 
 
 
#ifdef __riscv_32e
 
  misa_cc |= 1 << CSR_MISA_E_EXT;
 
#else
 
  misa_cc |= 1 << CSR_MISA_I_EXT;
 
#endif
 
 
 
#ifdef __riscv_mul
 
  misa_cc |= 1 << CSR_MISA_M_EXT;
 
#endif
 
 
 
#if (__riscv_xlen == 32)
 
  misa_cc |= 1 << CSR_MISA_MXL_LO_EXT;
 
#elif (__riscv_xlen == 64)
 
  misa_cc |= 2 << CSR_MISA_MXL_LO_EXT;
 
#else
 
  misa_cc |= 3 << CSR_MISA_MXL_LO_EXT;
 
#endif
 
 
 
  return misa_cc;
 
}
 
 
 
 
 
/**********************************************************************//**
 
 * NEORV32 runtime environment: Check required ISA extensions (via compiler flags) against available ISA extensions (via MISA csr).
 
 *
 
 * @param[in] silent Show error message (via neorv32.uart) if isa_sw > isa_hw when != 0.
 
 * @return MISA content according to compiler configuration.
 
 **************************************************************************/
 
int neorv32_rte_check_isa(int silent) {
 
 
 
  uint32_t misa_sw = neorv32_rte_get_compiler_isa();
 
  uint32_t misa_hw = neorv32_cpu_csr_read(CSR_MISA);
 
 
 
  // mask hardware features that are not used by software
 
  uint32_t check = misa_hw & misa_sw;
 
 
 
  //
 
  if (check == misa_sw) {
 
    return 0;
 
  }
 
  else {
 
    if (silent == 0) {
 
      neorv32_uart_printf("\nWARNING! SW_ISA (features required) vs HW_ISA (features available) mismatch!\n"
 
                          "SW_ISA = 0x%x (compiler flags)\n"
 
                          "HW_ISA = 0x%x (misa csr)\n\n", misa_sw, misa_hw);
 
    }
 
    return 1;
 
  }
 
}
 
 
 
 
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