OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_rte.c] - Diff between revs 65 and 66

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 65 Rev 66
Line 200... Line 200...
 
 
  if (neorv32_uart0_available() == 0) {
  if (neorv32_uart0_available() == 0) {
    return; // handler cannot output anything if UART0 is not implemented
    return; // handler cannot output anything if UART0 is not implemented
  }
  }
 
 
  char tmp;
 
 
 
  // intro
  // intro
  neorv32_uart0_print("<RTE> ");
  neorv32_uart0_print("<RTE> ");
 
 
  // cause
  // cause
  register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
  register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
  tmp = (char)(trap_cause & 0xf);
  register char tmp = (char)(trap_cause & 0xf);
  if (tmp >= 10) {
  if (tmp >= 10) {
    tmp = 'a' + (tmp - 10);
    tmp = 'a' + (tmp - 10);
  }
  }
  else {
  else {
    tmp = '0' + tmp;
    tmp = '0' + tmp;
Line 247... Line 245...
    case TRAP_CODE_FIRQ_14:
    case TRAP_CODE_FIRQ_14:
    case TRAP_CODE_FIRQ_15:      neorv32_uart0_print("Fast interrupt "); neorv32_uart0_putc(tmp); break;
    case TRAP_CODE_FIRQ_15:      neorv32_uart0_print("Fast interrupt "); neorv32_uart0_putc(tmp); break;
    default:                     neorv32_uart0_print("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break;
    default:                     neorv32_uart0_print("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break;
  }
  }
 
 
 
  // check cause if bus access fault exception
 
  if ((trap_cause == TRAP_CODE_I_ACCESS) || (trap_cause == TRAP_CODE_L_ACCESS) || (trap_cause == TRAP_CODE_S_ACCESS)) {
 
    register uint32_t bus_err = NEORV32_BUSKEEPER.CTRL;
 
    if (bus_err & (1<<BUSKEEPER_ERR_FLAG)) { // exception caused by bus system?
 
      if (bus_err & (1<<BUSKEEPER_ERR_TYPE)) {
 
        neorv32_uart0_print(" [TIMEOUT_ERR]");
 
      }
 
      else {
 
        neorv32_uart0_print(" [DEVICE_ERR]");
 
      }
 
    }
 
    else { // exception was not caused by bus system -> has to be caused by PMP rule violation
 
      neorv32_uart0_print(" [PMP_ERR]");
 
    }
 
  }
 
 
  // instruction address
  // instruction address
  neorv32_uart0_print(" @ PC=");
  neorv32_uart0_print(" @ PC=");
  __neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MSCRATCH)); // rte core stores actual mepc to mscratch
  __neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MSCRATCH)); // rte core stores original mepc to mscratch
 
 
  // additional info
  // additional info
  neorv32_uart0_print(", MTVAL=");
  neorv32_uart0_print(", MTVAL=");
  __neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MTVAL));
  __neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MTVAL));
  neorv32_uart0_print(" </RTE>");
  neorv32_uart0_print(" </RTE>");
Line 322... Line 336...
  // Z* CPU extensions
  // Z* CPU extensions
  tmp = NEORV32_SYSINFO.CPU;
  tmp = NEORV32_SYSINFO.CPU;
  if (tmp & (1<<SYSINFO_CPU_ZICSR)) {
  if (tmp & (1<<SYSINFO_CPU_ZICSR)) {
    neorv32_uart0_printf("Zicsr ");
    neorv32_uart0_printf("Zicsr ");
  }
  }
 
  if (tmp & (1<<SYSINFO_CPU_ZICNTR)) {
 
    neorv32_uart0_printf("Zicntr ");
 
  }
 
  if (tmp & (1<<SYSINFO_CPU_ZIHPM)) {
 
    neorv32_uart0_printf("Zihpm ");
 
  }
  if (tmp & (1<<SYSINFO_CPU_ZIFENCEI)) {
  if (tmp & (1<<SYSINFO_CPU_ZIFENCEI)) {
    neorv32_uart0_printf("Zifencei ");
    neorv32_uart0_printf("Zifencei ");
  }
  }
  if (tmp & (1<<SYSINFO_CPU_ZMMUL)) {
  if (tmp & (1<<SYSINFO_CPU_ZMMUL)) {
    neorv32_uart0_printf("Zmmul ");
    neorv32_uart0_printf("Zmmul ");
  }
  }
  if (tmp & (1<<SYSINFO_CPU_ZBB)) {
 
    neorv32_uart0_printf("Zbb ");
 
  }
 
 
 
  if (tmp & (1<<SYSINFO_CPU_ZFINX)) {
  if (tmp & (1<<SYSINFO_CPU_ZFINX)) {
    neorv32_uart0_printf("Zfinx ");
    neorv32_uart0_printf("Zfinx ");
  }
  }
  if (tmp & (1<<SYSINFO_CPU_ZXNOCNT)) {
 
    neorv32_uart0_printf("Zxnocnt(!) ");
 
  }
 
  if (tmp & (1<<SYSINFO_CPU_ZXSCNT)) {
  if (tmp & (1<<SYSINFO_CPU_ZXSCNT)) {
    neorv32_uart0_printf("Zxscnt(!) ");
    neorv32_uart0_printf("Zxscnt(!) ");
  }
  }
 
 
  if (tmp & (1<<SYSINFO_CPU_DEBUGMODE)) {
  if (tmp & (1<<SYSINFO_CPU_DEBUGMODE)) {
    neorv32_uart0_printf("Debug-Mode ");
    neorv32_uart0_printf("Debug ");
  }
  }
 
 
  if (tmp & (1<<SYSINFO_CPU_FASTMUL)) {
  if (tmp & (1<<SYSINFO_CPU_FASTMUL)) {
    neorv32_uart0_printf("FAST_MUL ");
    neorv32_uart0_printf("FAST_MUL ");
  }
  }
  if (tmp & (1<<SYSINFO_CPU_FASTSHIFT)) {
  if (tmp & (1<<SYSINFO_CPU_FASTSHIFT)) {
    neorv32_uart0_printf("FAST_SHIFT ");
    neorv32_uart0_printf("FAST_SHIFT ");
Line 362... Line 375...
  }
  }
  else {
  else {
    neorv32_uart0_printf("not implemented\n");
    neorv32_uart0_printf("not implemented\n");
  }
  }
 
 
  // check hardware performance monitors
 
  neorv32_uart0_printf("HPM Counters:      %u counters, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size());
 
 
 
 
 
  // Memory configuration
  // Memory configuration
  neorv32_uart0_printf("\n=== << Memory System >> ===\n");
  neorv32_uart0_printf("\n=== << Memory System >> ===\n");
 
 
  neorv32_uart0_printf("Boot Config.:         Boot ");
  neorv32_uart0_printf("Boot Config.:         Boot ");

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.