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Line 46... |
* The >private< trap vector look-up table of the NEORV32 RTE.
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* The >private< trap vector look-up table of the NEORV32 RTE.
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**************************************************************************/
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**************************************************************************/
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static uint32_t __neorv32_rte_vector_lut[NEORV32_RTE_NUM_TRAPS] __attribute__((unused)); // trap handler vector table
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static uint32_t __neorv32_rte_vector_lut[NEORV32_RTE_NUM_TRAPS] __attribute__((unused)); // trap handler vector table
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// private functions
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// private functions
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static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16)));
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static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(4)));
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static void __neorv32_rte_debug_exc_handler(void);
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static void __neorv32_rte_debug_exc_handler(void);
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static void __neorv32_rte_print_true_false(int state);
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static void __neorv32_rte_print_true_false(int state);
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static void __neorv32_rte_print_checkbox(int state);
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static void __neorv32_rte_print_checkbox(int state);
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static void __neorv32_rte_print_hex_word(uint32_t num);
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static void __neorv32_rte_print_hex_word(uint32_t num);
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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**************************************************************************/
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**************************************************************************/
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void neorv32_rte_setup(void) {
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void neorv32_rte_setup(void) {
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// configure trap handler base address
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// configure trap handler base address
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uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
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neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&__neorv32_rte_core));
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neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
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// install debug handler for all sources
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// install debug handler for all sources
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uint8_t id;
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uint8_t id;
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for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
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for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
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neorv32_rte_exception_uninstall(id); // this will configure the debug handler
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neorv32_rte_exception_uninstall(id); // this will configure the debug handler
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}
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}
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// clear BUSKEEPER error flags
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NEORV32_BUSKEEPER.CTRL = 0;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Install exception handler function to NEORV32 runtime environment.
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* Install exception handler function to NEORV32 runtime environment.
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**************************************************************************/
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**************************************************************************/
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int neorv32_rte_exception_uninstall(uint8_t id) {
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int neorv32_rte_exception_uninstall(uint8_t id) {
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// id valid?
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// id valid?
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if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) {
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if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered
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__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidentally triggered
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return 0;
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return 0;
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}
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}
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return 1;
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return 1;
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}
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}
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* @note This function must no be explicitly used by the user.
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* @note This function must no be explicitly used by the user.
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* @note The RTE core uses mscratch CSR to store the trap-causing mepc for further (user-defined) processing.
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* @note The RTE core uses mscratch CSR to store the trap-causing mepc for further (user-defined) processing.
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*
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*
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* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute!
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* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute!
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**************************************************************************/
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**************************************************************************/
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static void __attribute__((__interrupt__)) __attribute__((aligned(16))) __neorv32_rte_core(void) {
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static void __attribute__((__interrupt__)) __attribute__((aligned(4))) __neorv32_rte_core(void) {
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register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
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neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later
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neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later
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register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
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// compute return address
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// compute return address
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if (((int32_t)rte_mcause) >= 0) { // modify pc only if exception (MSB cleared)
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if (((int32_t)rte_mcause) >= 0) { // modify pc only if not interrupt (MSB cleared)
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// get low half word of faulting instruction
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// get low half word of faulting instruction
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register uint32_t rte_trap_inst;
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register uint32_t rte_trap_inst;
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (rte_trap_inst) : [input_i] "r" (rte_mepc));
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (rte_trap_inst) : [input_i] "r" (rte_mepc));
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// store new return address
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// store new return address
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neorv32_cpu_csr_write(CSR_MEPC, rte_mepc);
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neorv32_cpu_csr_write(CSR_MEPC, rte_mepc);
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}
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}
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// find according trap handler
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// find according trap handler
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register uint32_t rte_handler = (uint32_t)(&__neorv32_rte_debug_exc_handler);
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register uint32_t rte_handler;
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switch (rte_mcause) {
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switch (rte_mcause) {
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case TRAP_CODE_I_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
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case TRAP_CODE_I_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
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case TRAP_CODE_I_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
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case TRAP_CODE_I_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
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case TRAP_CODE_I_ILLEGAL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
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case TRAP_CODE_I_ILLEGAL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
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case TRAP_CODE_BREAKPOINT: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
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case TRAP_CODE_BREAKPOINT: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
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case TRAP_CODE_FIRQ_11: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_11]; break;
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case TRAP_CODE_FIRQ_11: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_11]; break;
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case TRAP_CODE_FIRQ_12: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_12]; break;
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case TRAP_CODE_FIRQ_12: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_12]; break;
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case TRAP_CODE_FIRQ_13: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break;
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case TRAP_CODE_FIRQ_13: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break;
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case TRAP_CODE_FIRQ_14: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break;
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case TRAP_CODE_FIRQ_14: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break;
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case TRAP_CODE_FIRQ_15: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break;
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case TRAP_CODE_FIRQ_15: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break;
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default: break;
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default: rte_handler = (uint32_t)(&__neorv32_rte_debug_exc_handler); break;
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}
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}
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// execute handler
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// execute handler
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void (*handler_pnt)(void);
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void (*handler_pnt)(void);
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handler_pnt = (void*)rte_handler;
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handler_pnt = (void*)rte_handler;
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Line 730... |
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/**********************************************************************//**
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/**********************************************************************//**
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* NEORV32 runtime environment: Check required ISA extensions (via compiler flags) against available ISA extensions (via MISA csr).
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* NEORV32 runtime environment: Check required ISA extensions (via compiler flags) against available ISA extensions (via MISA csr).
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*
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*
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* @param[in] silent Show error message (via neorv32.uart) if isa_sw > isa_hw when != 0.
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* @param[in] silent Show error message (via neorv32.uart) if isa_sw > isa_hw when = 0.
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* @return MISA content according to compiler configuration.
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* @return MISA content according to compiler configuration.
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**************************************************************************/
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**************************************************************************/
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int neorv32_rte_check_isa(int silent) {
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int neorv32_rte_check_isa(int silent) {
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uint32_t misa_sw = neorv32_rte_get_compiler_isa();
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uint32_t misa_sw = neorv32_rte_get_compiler_isa();
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| Line 744... |
Line 746... |
//
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//
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if (check == misa_sw) {
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if (check == misa_sw) {
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return 0;
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return 0;
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}
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}
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else {
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else {
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if ((silent == 0) || (neorv32_uart0_available() == 0)) {
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if ((silent == 0) && (neorv32_uart0_available() != 0)) {
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neorv32_uart0_printf("\nWARNING! SW_ISA (features required) vs HW_ISA (features available) mismatch!\n"
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neorv32_uart0_printf("\nWARNING! SW_ISA (features required) vs HW_ISA (features available) mismatch!\n"
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"SW_ISA = 0x%x (compiler flags)\n"
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"SW_ISA = 0x%x (compiler flags)\n"
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"HW_ISA = 0x%x (misa csr)\n\n", misa_sw, misa_hw);
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"HW_ISA = 0x%x (misa csr)\n\n", misa_sw, misa_hw);
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}
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}
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return 1;
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return 1;
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