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* Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CT_enum.
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* Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CT_enum.
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*
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*
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* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
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* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
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* @param[in] clk_polarity Idle clock polarity (0, 1).
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* @param[in] clk_polarity Idle clock polarity (0, 1).
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* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
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* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
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* @param[in] irq_en Enable transfer-done interrupt when 1.
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**************************************************************************/
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**************************************************************************/
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void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size, uint8_t irq_en) {
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void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) {
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SPI_CT = 0; // reset
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SPI_CT = 0; // reset
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uint32_t ct_enable = 1;
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uint32_t ct_enable = 1;
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ct_enable = ct_enable << SPI_CT_EN;
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ct_enable = ct_enable << SPI_CT_EN;
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ct_polarity = ct_polarity << SPI_CT_CPHA;
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ct_polarity = ct_polarity << SPI_CT_CPHA;
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uint32_t ct_size = (uint32_t)(data_size & 0x03);
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uint32_t ct_size = (uint32_t)(data_size & 0x03);
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ct_size = ct_size << SPI_CT_SIZE0;
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ct_size = ct_size << SPI_CT_SIZE0;
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uint32_t ct_irq = (uint32_t)(irq_en & 0x01);
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SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size;
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ct_irq = ct_irq << SPI_CT_IRQ_EN;
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SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size | ct_irq;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Disable and SPI controller.
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* Disable and SPI controller.
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