| Line 50... |
Line 50... |
*
|
*
|
* @return 0 if SPI was not synthesized, 1 if SPI is available.
|
* @return 0 if SPI was not synthesized, 1 if SPI is available.
|
**************************************************************************/
|
**************************************************************************/
|
int neorv32_spi_available(void) {
|
int neorv32_spi_available(void) {
|
|
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_SPI)) {
|
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_SPI)) {
|
return 1;
|
return 1;
|
}
|
}
|
else {
|
else {
|
return 0;
|
return 0;
|
}
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}
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}
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}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CT_enum.
|
* Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CTRL_enum.
|
*
|
*
|
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
|
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
|
* @param[in] clk_polarity Idle clock polarity (0, 1).
|
* @param[in] clk_polarity Idle clock polarity (0, 1).
|
* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
|
* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) {
|
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) {
|
|
|
SPI_CT = 0; // reset
|
NEORV32_SPI.CTRL = 0; // reset
|
|
|
uint32_t ct_enable = 1;
|
uint32_t ct_enable = 1;
|
ct_enable = ct_enable << SPI_CT_EN;
|
ct_enable = ct_enable << SPI_CTRL_EN;
|
|
|
uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
|
uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
|
ct_prsc = ct_prsc << SPI_CT_PRSC0;
|
ct_prsc = ct_prsc << SPI_CTRL_PRSC0;
|
|
|
uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01);
|
uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01);
|
ct_polarity = ct_polarity << SPI_CT_CPHA;
|
ct_polarity = ct_polarity << SPI_CTRL_CPHA;
|
|
|
uint32_t ct_size = (uint32_t)(data_size & 0x03);
|
uint32_t ct_size = (uint32_t)(data_size & 0x03);
|
ct_size = ct_size << SPI_CT_SIZE0;
|
ct_size = ct_size << SPI_CTRL_SIZE0;
|
|
|
SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size;
|
NEORV32_SPI.CTRL = ct_enable | ct_prsc | ct_polarity | ct_size;
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Disable SPI controller.
|
* Disable SPI controller.
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_spi_disable(void) {
|
void neorv32_spi_disable(void) {
|
|
|
SPI_CT &= ~((uint32_t)(1 << SPI_CT_EN));
|
NEORV32_SPI.CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN));
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Enable SPI controller.
|
* Enable SPI controller.
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_spi_enable(void) {
|
void neorv32_spi_enable(void) {
|
|
|
SPI_CT |= ((uint32_t)(1 << SPI_CT_EN));
|
NEORV32_SPI.CTRL |= ((uint32_t)(1 << SPI_CTRL_EN));
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Activate SPI chip select signal.
|
* Activate SPI chip select signal.
|
| Line 114... |
Line 114... |
* @param cs Chip select line to activate (0..7).
|
* @param cs Chip select line to activate (0..7).
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_spi_cs_en(uint8_t cs) {
|
void neorv32_spi_cs_en(uint8_t cs) {
|
|
|
uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
|
uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
|
cs_mask = cs_mask << SPI_CT_CS0;
|
cs_mask = cs_mask << SPI_CTRL_CS0;
|
SPI_CT |= cs_mask;
|
NEORV32_SPI.CTRL |= cs_mask;
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Deactivate SPI chip select signal.
|
* Deactivate SPI chip select signal.
|
| Line 129... |
Line 129... |
* @param cs Chip select line to deactivate (0..7).
|
* @param cs Chip select line to deactivate (0..7).
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_spi_cs_dis(uint8_t cs) {
|
void neorv32_spi_cs_dis(uint8_t cs) {
|
|
|
uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
|
uint32_t cs_mask = (uint32_t)(1 << (cs & 0x07));
|
cs_mask = cs_mask << SPI_CT_CS0;
|
cs_mask = cs_mask << SPI_CTRL_CS0;
|
SPI_CT &= ~cs_mask;
|
NEORV32_SPI.CTRL &= ~cs_mask;
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Initiate SPI transfer.
|
* Initiate SPI transfer.
|
| Line 146... |
Line 146... |
* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
|
* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
|
* @return Receive data (8/16/24/32-bit, LSB-aligned).
|
* @return Receive data (8/16/24/32-bit, LSB-aligned).
|
**************************************************************************/
|
**************************************************************************/
|
uint32_t neorv32_spi_trans(uint32_t tx_data) {
|
uint32_t neorv32_spi_trans(uint32_t tx_data) {
|
|
|
SPI_DATA = tx_data; // trigger transfer
|
NEORV32_SPI.DATA = tx_data; // trigger transfer
|
while((SPI_CT & (1<<SPI_CT_BUSY)) != 0); // wait for current transfer to finish
|
while((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish
|
|
|
return SPI_DATA;
|
return NEORV32_SPI.DATA;
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Check if SPI transceiver is busy.
|
* Check if SPI transceiver is busy.
|
| Line 162... |
Line 162... |
*
|
*
|
* @return 0 if idle, 1 if busy
|
* @return 0 if idle, 1 if busy
|
**************************************************************************/
|
**************************************************************************/
|
int neorv32_spi_busy(void) {
|
int neorv32_spi_busy(void) {
|
|
|
if ((SPI_CT & (1<<SPI_CT_BUSY)) != 0) {
|
if ((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
|
return 1;
|
return 1;
|
}
|
}
|
return 0;
|
return 0;
|
}
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
