OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_trng.c] - Diff between revs 47 and 64

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 47 Rev 64
Line 50... Line 50...
 *
 *
 * @return 0 if TRNG was not synthesized, 1 if TRNG is available.
 * @return 0 if TRNG was not synthesized, 1 if TRNG is available.
 **************************************************************************/
 **************************************************************************/
int neorv32_trng_available(void) {
int neorv32_trng_available(void) {
 
 
  if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_TRNG)) {
  if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_TRNG)) {
    return 1;
    return 1;
  }
  }
  else {
  else {
    return 0;
    return 0;
  }
  }
}
}
 
 
 
 
/**********************************************************************//**
/**********************************************************************//**
 * Enable true random number generator. The TRNG control register bits are listed in #NEORV32_TRNG_CT_enum.
 * Enable true random number generator. The TRNG control register bits are listed in #NEORV32_TRNG_CTRL_enum.
 **************************************************************************/
 **************************************************************************/
void neorv32_trng_enable(void) {
void neorv32_trng_enable(void) {
 
 
  int i;
  int i;
 
 
  TRNG_CT = 0; // reset
  NEORV32_TRNG.CTRL = 0; // reset
 
 
  for (i=0; i<256; i++) {
  for (i=0; i<256; i++) {
    asm volatile ("nop");
    asm volatile ("nop");
  }
  }
 
 
  TRNG_CT = 1 << TRNG_CT_EN; // activate
  NEORV32_TRNG.CTRL = 1 << TRNG_CTRL_EN; // activate
 
 
  for (i=0; i<256; i++) {
  for (i=0; i<256; i++) {
    asm volatile ("nop");
    asm volatile ("nop");
  }
  }
}
}
Line 85... Line 85...
/**********************************************************************//**
/**********************************************************************//**
 * Disable true random number generator.
 * Disable true random number generator.
 **************************************************************************/
 **************************************************************************/
void neorv32_trng_disable(void) {
void neorv32_trng_disable(void) {
 
 
  TRNG_CT = 0;
  NEORV32_TRNG.CTRL = 0;
}
}
 
 
 
 
/**********************************************************************//**
/**********************************************************************//**
 * Get random data byte from TRNG.
 * Get random data byte from TRNG.
Line 102... Line 102...
  const int retries = 3;
  const int retries = 3;
  int i;
  int i;
  uint32_t ct_reg;
  uint32_t ct_reg;
 
 
  for (i=0; i<retries; i++) {
  for (i=0; i<retries; i++) {
    ct_reg = TRNG_CT;
    ct_reg = NEORV32_TRNG.CTRL;
 
 
    if ((ct_reg & (1<<TRNG_CT_VALID)) == 0) { // output data valid?
    if ((ct_reg & (1<<TRNG_CTRL_VALID)) == 0) { // output data valid?
      continue;
      continue;
    }
    }
 
 
    *data = (uint8_t)(ct_reg >> TRNG_CT_DATA_LSB);
    *data = (uint8_t)(ct_reg >> TRNG_CTRL_DATA_LSB);
    return 0; // valid data
    return 0; // valid data
  }
  }
 
 
  return -1; // no valid data available
  return -1; // no valid data available
}
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.