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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_twi.c] - Diff between revs 23 and 35

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Rev 23 Rev 35
Line 64... Line 64...
/**********************************************************************//**
/**********************************************************************//**
 * Enable and configure TWI controller. The TWI control register bits are listed in #NEORV32_TWI_CT_enum.
 * Enable and configure TWI controller. The TWI control register bits are listed in #NEORV32_TWI_CT_enum.
 *
 *
 * @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
 * @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
 * @param[in] irq_en Enable transfer-done interrupt when 1.
 * @param[in] irq_en Enable transfer-done interrupt when 1.
 
 * @param[in] ckst_en Enable clock-stretching by peripherals when 1.
 **************************************************************************/
 **************************************************************************/
void neorv32_twi_setup(uint8_t prsc, uint8_t irq_en) {
void neorv32_twi_setup(uint8_t prsc, uint8_t irq_en, uint8_t ckst_en) {
 
 
  TWI_CT = 0; // reset
  TWI_CT = 0; // reset
 
 
  uint32_t ct_enable = 1;
  uint32_t ct_enable = 1;
  ct_enable = ct_enable << TWI_CT_EN;
  ct_enable = ct_enable << TWI_CT_EN;
Line 78... Line 79...
  ct_prsc = ct_prsc << TWI_CT_PRSC0;
  ct_prsc = ct_prsc << TWI_CT_PRSC0;
 
 
  uint32_t ct_irq = (uint32_t)(irq_en & 0x01);
  uint32_t ct_irq = (uint32_t)(irq_en & 0x01);
  ct_irq = ct_irq << TWI_CT_IRQ_EN;
  ct_irq = ct_irq << TWI_CT_IRQ_EN;
 
 
  TWI_CT = ct_enable | ct_prsc | ct_irq;
  uint32_t ct_cksten = (uint32_t)(ckst_en & 0x01);
 
  ct_cksten = ct_cksten << TWI_CT_CKSTEN;
 
 
 
  TWI_CT = ct_enable | ct_prsc | ct_irq | ct_cksten;
}
}
 
 
 
 
/**********************************************************************//**
/**********************************************************************//**
 * Disable TWI controller.
 * Disable TWI controller.

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