OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_uart.c] - Diff between revs 44 and 47

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 44 Rev 47
Line 69... Line 69...
 
 
 
 
/**********************************************************************//**
/**********************************************************************//**
 * Enable and configure UART.
 * Enable and configure UART.
 *
 *
 * @warning The 'UART_SIM_MODE' compiler flag will configure UART for simulation mode: all UART TX data will be redirected to simulation output. Use this for simulations only!
 * @note The 'UART_SIM_MODE' compiler flag will configure UART for simulation mode: all UART TX data will be redirected to simulation output. Use this for simulations only!
 * @warning To enable simulation mode add <USER_FLAGS+=-DUART_SIM_MODE> when compiling.
 * @note To enable simulation mode add <USER_FLAGS+=-DUART_SIM_MODE> when compiling.
 
 *
 
 * @warning The baud rate is computed using INTEGER operations (truncation errors might occur).
 *
 *
 * @param[in] baudrate Targeted BAUD rate (e.g. 9600).
 * @param[in] baudrate Targeted BAUD rate (e.g. 9600).
 * @param[in] parity PArity configuration (00=off, 10=even, 11=odd).
 * @param[in] parity PArity configuration (00=off, 10=even, 11=odd).
 * @param[in] rx_irq Enable RX interrupt (data received) when 1.
 * @param[in] rx_irq Enable RX interrupt (data received) when 1.
 * @param[in] tx_irq Enable TX interrupt (transmission done) when 1.
 * @param[in] tx_irq Enable TX interrupt (transmission done) when 1.
Line 97... Line 99...
    clock -= 2*baudrate;
    clock -= 2*baudrate;
    i++;
    i++;
  }
  }
#endif
#endif
 
 
  // find clock prsc
  // find baud prescaler (12-bit wide))
  while (i >= 0x0fff) {
  while (i >= 0x0fff) {
    if ((p == 2) || (p == 4))
    if ((p == 2) || (p == 4))
      i >>= 3;
      i >>= 3;
    else
    else
      i >>= 1;
      i >>= 1;
    p++;
    p++;
  }
  }
 
 
  uint32_t prsc = (uint32_t)p;
  uint32_t clk_prsc = (uint32_t)p;
  prsc = prsc << UART_CT_PRSC0;
  clk_prsc = clk_prsc << UART_CT_PRSC0;
 
 
  uint32_t baud = (uint32_t)i;
  uint32_t baud_prsc = (uint32_t)i;
  baud = baud << UART_CT_BAUD00;
  baud_prsc = baud_prsc - 1;
 
  baud_prsc = baud_prsc << UART_CT_BAUD00;
 
 
  uint32_t uart_en = 1;
  uint32_t uart_en = 1;
  uart_en = uart_en << UART_CT_EN;
  uart_en = uart_en << UART_CT_EN;
 
 
  uint32_t parity_config = (uint32_t)(parity & 3);
  uint32_t parity_config = (uint32_t)(parity & 3);
Line 133... Line 136...
  uint32_t sim_mode = 1 << UART_CT_SIM_MODE;
  uint32_t sim_mode = 1 << UART_CT_SIM_MODE;
#else
#else
  uint32_t sim_mode = 0;
  uint32_t sim_mode = 0;
#endif
#endif
 
 
  UART_CT = prsc | baud | uart_en | parity_config | rx_irq_en | tx_irq_en | sim_mode;
  UART_CT = clk_prsc | baud_prsc | uart_en | parity_config | rx_irq_en | tx_irq_en | sim_mode;
}
}
 
 
 
 
/**********************************************************************//**
/**********************************************************************//**
 * Disable UART.
 * Disable UART.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.