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Line 50... |
*
|
*
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* @return 0 if WDT was not synthesized, 1 if WDT is available.
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* @return 0 if WDT was not synthesized, 1 if WDT is available.
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**************************************************************************/
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**************************************************************************/
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int neorv32_wdt_available(void) {
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int neorv32_wdt_available(void) {
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|
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if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_WDT)) {
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if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_WDT)) {
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return 1;
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return 1;
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}
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}
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else {
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else {
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return 0;
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return 0;
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}
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}
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Configure and enable watchdog timer. The WDT control register bits are listed in #NEORV32_WDT_CT_enum.
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* Configure and enable watchdog timer. The WDT control register bits are listed in #NEORV32_WDT_CTRL_enum.
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*
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*
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* @param[in] prsc Clock prescaler to select timeout interval. See #NEORV32_CLOCK_PRSC_enum.
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* @param[in] prsc Clock prescaler to select timeout interval. See #NEORV32_CLOCK_PRSC_enum.
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* @param[in] mode Trigger system reset on timeout when 1, trigger interrupt on timeout when 0.
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* @param[in] mode Trigger system reset on timeout when 1, trigger interrupt on timeout when 0.
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* @param[in] lock Control register will be locked when 1 (until next reset).
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* @param[in] lock Control register will be locked when 1 (until next reset).
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**************************************************************************/
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**************************************************************************/
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void neorv32_wdt_setup(uint8_t prsc, uint8_t mode, uint8_t lock) {
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void neorv32_wdt_setup(uint8_t prsc, uint8_t mode, uint8_t lock) {
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|
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WDT_CT = (1 << WDT_CT_RESET); // reset WDT counter
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NEORV32_WDT.CTRL = (1 << WDT_CTRL_RESET); // reset WDT counter
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|
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uint32_t prsc_int = (uint32_t)(prsc & 0x07);
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uint32_t prsc_int = (uint32_t)(prsc & 0x07);
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prsc_int = prsc_int << WDT_CT_CLK_SEL0;
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prsc_int = prsc_int << WDT_CTRL_CLK_SEL0;
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|
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uint32_t mode_int = (uint32_t)(mode & 0x01);
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uint32_t mode_int = (uint32_t)(mode & 0x01);
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mode_int = mode_int << WDT_CT_MODE;
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mode_int = mode_int << WDT_CTRL_MODE;
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|
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uint32_t lock_int = (uint32_t)(lock & 0x01);
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uint32_t lock_int = (uint32_t)(lock & 0x01);
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lock_int = lock_int << WDT_CT_LOCK;
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lock_int = lock_int << WDT_CTRL_LOCK;
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|
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const uint32_t enable = (uint32_t)(1 << WDT_CT_EN);
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const uint32_t enable = (uint32_t)(1 << WDT_CTRL_EN);
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|
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// update WDT control register
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// update WDT control register
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WDT_CT = enable | mode_int | prsc_int | lock_int;
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NEORV32_WDT.CTRL = enable | mode_int | prsc_int | lock_int;
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}
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}
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|
|
|
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/**********************************************************************//**
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/**********************************************************************//**
|
* Disable watchdog timer.
|
* Disable watchdog timer.
|
*
|
*
|
* @return Returns 0 if WDT is really deactivated, -1 otherwise.
|
* @return Returns 0 if WDT is really deactivated, -1 otherwise.
|
**************************************************************************/
|
**************************************************************************/
|
int neorv32_wdt_disable(void) {
|
int neorv32_wdt_disable(void) {
|
|
|
WDT_CT = 0;
|
NEORV32_WDT.CTRL = 0;
|
|
|
// check if wdt is really off
|
// check if wdt is really off
|
if (WDT_CT & (1 << WDT_CT_EN)) {
|
if (NEORV32_WDT.CTRL & (1 << WDT_CTRL_EN)) {
|
return -1; // WDT still active
|
return -1; // WDT still active
|
}
|
}
|
else {
|
else {
|
return 0;
|
return 0;
|
}
|
}
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| Line 110... |
Line 110... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* Reset (running) watchdog.
|
* Reset (running) watchdog.
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_wdt_reset(void) {
|
void neorv32_wdt_reset(void) {
|
|
|
WDT_CT = WDT_CT | (1 << WDT_CT_RESET);
|
NEORV32_WDT.CTRL = NEORV32_WDT.CTRL | (1 << WDT_CTRL_RESET);
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* Get cause of last system reset.
|
* Get cause of last system reset.
|
*
|
*
|
* @return Cause of last reset/IRQ (0: external reset, 1: watchdog timeout).
|
* @return Cause of last reset/IRQ (0: external reset, 1: watchdog timeout).
|
**************************************************************************/
|
**************************************************************************/
|
int neorv32_wdt_get_cause(void) {
|
int neorv32_wdt_get_cause(void) {
|
|
|
if (WDT_CT & (1 << WDT_CT_RCAUSE)) { // reset caused by watchdog
|
if (NEORV32_WDT.CTRL & (1 << WDT_CTRL_RCAUSE)) { // reset caused by watchdog
|
return 1;
|
return 1;
|
}
|
}
|
else { // external reset
|
else { // external reset
|
return 0;
|
return 0;
|
}
|
}
|
| Line 135... |
Line 135... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* Force immediate watchdog action (reset/IRQ).
|
* Force immediate watchdog action (reset/IRQ).
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_wdt_force(void) {
|
void neorv32_wdt_force(void) {
|
|
|
WDT_CT = WDT_CT | (1 << WDT_CT_FORCE);
|
NEORV32_WDT.CTRL = NEORV32_WDT.CTRL | (1 << WDT_CTRL_FORCE);
|
}
|
}
|
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No newline at end of file
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No newline at end of file
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