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[/] [next186/] [trunk/] [Next186_ALU.v] - Diff between revs 9 and 12
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| Rev 9 |
Rev 12 |
| Line 89... |
Line 89... |
output reg [15:0]FOUT,
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output reg [15:0]FOUT,
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output reg [15:0]ALUOUT,
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output reg [15:0]ALUOUT,
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output reg ALUCONT,
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output reg ALUCONT,
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output NULLSHIFT,
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output NULLSHIFT,
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output COUT,
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output COUT,
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output SOUT,
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input [2:0]STAGE,
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input [2:0]STAGE,
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input CLK
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input CLK
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);
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);
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reg CPLOP2;
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reg CPLOP2;
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| Line 117... |
Line 116... |
// ADDER
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// ADDER
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assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;
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assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;
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assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;
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assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;
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assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;
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assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;
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assign COUT = (WORD ? SC16OUT : SC8OUT) ^ CPLOP2;
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assign COUT = (WORD ? SC16OUT : SC8OUT) ^ CPLOP2;
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assign SOUT = WORD ? SUMOUT[15] : SUMOUT[7];
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// SHIFTER
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// SHIFTER
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reg [4:0]SHNOPT; // optimized shift
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reg [4:0]SHNOPT; // optimized shift
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wire [4:0]SHN = {STAGE[2:1] ^ SHNOPT[4:3], SHNOPT[2:0]};
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wire [4:0]SHN = {STAGE[2:1] ^ SHNOPT[4:3], SHNOPT[2:0]};
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assign NULLSHIFT = ~|SHNOPT;
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assign NULLSHIFT = ~|SHNOPT;
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