| Line 57... |
Line 57... |
// 03Apr2013 - fix RET n alignment bug
|
// 03Apr2013 - fix RET n alignment bug
|
// 04Apr2013 - fix TRAP interrupt acknowledge
|
// 04Apr2013 - fix TRAP interrupt acknowledge
|
// 12Apr2013 - fix IDIV when Q=0
|
// 12Apr2013 - fix IDIV when Q=0
|
// 16May2013 - fix PUSHA SP pushed stack value, which should be the one before PUSHA
|
// 16May2013 - fix PUSHA SP pushed stack value, which should be the one before PUSHA
|
// 25May2013 - generate invalid opcode exception for MOV FS and GS
|
// 25May2013 - generate invalid opcode exception for MOV FS and GS
|
|
// 08Sep2016 - separate port address (PORT_ADDR)
|
|
// 15Sep2017 - implemented SALC undocumented instruction
|
///////////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////////
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
|
module Next186_CPU(
|
module Next186_CPU(
|
output [20:0] ADDR,
|
output [20:0]ADDR, // mem address
|
input [15:0] DIN,
|
output [15:0]PORT_ADDR, // port address
|
output [15:0] DOUT,
|
input [15:0]DIN, // mem/port data in
|
|
output [15:0]DOUT, // mem data out
|
|
output [15:0]POUT, // port data out
|
input CLK,
|
input CLK,
|
input CE,
|
input CE,
|
input INTR,
|
input INTR,
|
input NMI,
|
input NMI,
|
input RST,
|
input RST,
|
output reg MREQ,
|
output reg MREQ,
|
output wire IORQ,
|
output reg IORQ,
|
output reg INTA,
|
output reg INTA,
|
output reg WR,
|
output reg WR,
|
output reg WORD,
|
output reg WORD,
|
output LOCK,
|
output LOCK,
|
output [20:0]IADDR,
|
output [20:0]IADDR,
|
| Line 98... |
Line 102... |
wire [15:0]DI;
|
wire [15:0]DI;
|
wire [15:0]DX;
|
wire [15:0]DX;
|
wire [15:0]FLAGS;
|
wire [15:0]FLAGS;
|
wire [15:0]FIN;
|
wire [15:0]FIN;
|
wire [15:0]ALUOUT;
|
wire [15:0]ALUOUT;
|
|
wire [15:0]ALUOUTA;
|
wire [15:0]AIMM1;
|
wire [15:0]AIMM1;
|
reg [15:0]DIMM1;
|
reg [15:0]DIMM1;
|
wire [15:0]RS;
|
wire [15:0]RS;
|
wire [15:0]ADDR16;
|
wire [15:0]ADDR16;
|
wire [15:0]CS;
|
wire [15:0]CS;
|
| Line 149... |
Line 154... |
reg [2:0]IRQL;
|
reg [2:0]IRQL;
|
reg REPINT;
|
reg REPINT;
|
reg [5:0]ICODE1 = 23;
|
reg [5:0]ICODE1 = 23;
|
reg NULLSEG;
|
reg NULLSEG;
|
reg DIVOP;
|
reg DIVOP;
|
|
reg DIVIRQ;
|
|
reg AAMIRQ;
|
|
reg RCOUT;
|
|
|
// signals
|
// signals
|
assign IORQ = &EAC;
|
// assign IORQ = &EAC;
|
assign LOCK = CPUStatus[5];
|
assign LOCK = CPUStatus[5];
|
assign FLUSH = ~IPWSEL || (ISIZE == 3'b000);
|
assign FLUSH = ~IPWSEL || (ISIZE == 3'b000);
|
|
assign PORT_ADDR = FETCH[0][3] ? DX : {8'h00, FETCH[1]};
|
wire [15:0]IPADD = ISIZE == 3'b000 ? CRTIP : IP + ISIZE;
|
wire [15:0]IPADD = ISIZE == 3'b000 ? CRTIP : IP + ISIZE;
|
wire [15:0]IPIN = IPWSEL ? IPADD : ALUOUT;
|
wire [15:0]IPIN = IPWSEL ? IPADD : ALUOUTA;
|
wire [1:0]MOD = FETCH[1][7:6];
|
wire [1:0]MOD = FETCH[1][7:6];
|
wire [2:0]REG = FETCH[1][5:3];
|
wire [2:0]REG = FETCH[1][5:3];
|
wire [2:0]RM = FETCH[1][2:0];
|
wire [2:0]RM = FETCH[1][2:0];
|
wire USEBP = RM[1] && ~&RM;
|
wire USEBP = RM[1] && ~&RM;
|
wire POP = {EAC[3], EAC[1:0]} == 3'b101;
|
wire POP = {EAC[3], EAC[1:0]} == 3'b101;
|
| Line 239... |
Line 248... |
.FOUT(FIN),
|
.FOUT(FIN),
|
.ALUOP(ALUOP),
|
.ALUOP(ALUOP),
|
.EXOP(FETCH[1][5:3]),
|
.EXOP(FETCH[1][5:3]),
|
.FLAGOP(FETCH[0][3:0]),
|
.FLAGOP(FETCH[0][3:0]),
|
.ALUOUT(ALUOUT),
|
.ALUOUT(ALUOUT),
|
|
.ALUOUTA(ALUOUTA),
|
.WORD(WORD),
|
.WORD(WORD),
|
.ALUCONT(ALUCONT),
|
.ALUCONT(ALUCONT),
|
.NULLSHIFT(NULLSHIFT),
|
.NULLSHIFT(NULLSHIFT),
|
.STAGE(STAGE[2:0]),
|
.STAGE(STAGE[2:0]),
|
.INC2(&DISEL), // when DISEL == 2'b11, inc/dec value is 2 if WORD and 1 if ~WORD
|
.INC2(&DISEL), // when DISEL == 2'b11, inc/dec value is 2 if WORD and 1 if ~WORD
|
| Line 254... |
Line 264... |
.SP(SP),
|
.SP(SP),
|
.BX(BX),
|
.BX(BX),
|
.BP(NOBP ? 16'h0000 : BP),
|
.BP(NOBP ? 16'h0000 : BP),
|
.SI(SI),
|
.SI(SI),
|
.DI(DI),
|
.DI(DI),
|
.PIO(FETCH[0][3] ? DX : {8'h00, FETCH[1]}),
|
|
.TMP16(TMP16),
|
.TMP16(TMP16),
|
.AL(AX[7:0]),
|
.AL(AX[7:0]),
|
.AIMM(AEXT ? {{8{AIMM1[7]}}, AIMM1[7:0]} : (DISP16 ? AIMM1 : 16'h0000)),
|
.AIMM(AEXT ? {{8{AIMM1[7]}}, AIMM1[7:0]} : (DISP16 ? AIMM1 : 16'h0000)),
|
.ADDR16(ADDR16),
|
.ADDR16(ADDR16),
|
.EAC(EAC)
|
.EAC(EAC)
|
);
|
);
|
|
|
assign DOUT = DOSEL[1] ? DOSEL[0] ? AX : TMP16 : DOSEL[0] ? IPADD : ALUOUT;
|
assign POUT = DOSEL[0] ? AX : TMP16;
|
|
assign DOUT = DOSEL[1] ? POUT : DOSEL[0] ? IPADD : ALUOUT;
|
assign ADDR = {{NULLSEG ? 16'h0000 : RS} + {5'b00000, ADDR16_SP[15:4]}, ADDR16_SP[3:0]};
|
assign ADDR = {{NULLSEG ? 16'h0000 : RS} + {5'b00000, ADDR16_SP[15:4]}, ADDR16_SP[3:0]};
|
assign IADDR = {CS + {5'b00000, IPIN[15:4]}, IPIN[3:0]};
|
assign IADDR = {CS + {5'b00000, IPIN[15:4]}, IPIN[3:0]};
|
assign AIMM1 = ASEL ? {FETCH[3], FETCH[2]} : {FETCH[2], FETCH[1]};
|
assign AIMM1 = ASEL ? {FETCH[3], FETCH[2]} : {FETCH[2], FETCH[1]};
|
|
|
always @(posedge CLK)
|
always @(posedge CLK)
|
| Line 298... |
Line 308... |
FETCH[0] <= INSTR[7:0];
|
FETCH[0] <= INSTR[7:0];
|
STAGE <= 0;
|
STAGE <= 0;
|
CPUStatus[5:0] <= status[5:0];
|
CPUStatus[5:0] <= status[5:0];
|
ICODE1 <= ICODE(INSTR[7:0]);
|
ICODE1 <= ICODE(INSTR[7:0]);
|
end else begin // no interrupt, no fetch
|
end else begin // no interrupt, no fetch
|
STAGE <= STAGE + {DIVSTAGE, ALUSTAGE} + 1;
|
STAGE <= STAGE + {DIVSTAGE, ALUSTAGE} + 1'b1;
|
if(&DOSEL) {FETCH[3], FETCH[2]} <= |DISEL ? DIN : RB;
|
if(&DOSEL) {FETCH[3], FETCH[2]} <= |DISEL ? DIN : RB;
|
TZF <= FIN[6]; // zero flag for BOUND
|
TZF <= FIN[6]; // zero flag for BOUND
|
TLF <= FIN[7] != FIN[11]; // less flag for BOUND
|
TLF <= FIN[7] != FIN[11]; // less flag for BOUND
|
end
|
end
|
end
|
end
|
| Line 316... |
Line 326... |
end
|
end
|
if(~|STAGE[1:0]) DIVQSGN <= QSGN;
|
if(~|STAGE[1:0]) DIVQSGN <= QSGN;
|
RDIVEXC <= DIVOP & DIVEXC & ~IDIV; // bit 8/16 for unsigned DIV
|
RDIVEXC <= DIVOP & DIVEXC & ~IDIV; // bit 8/16 for unsigned DIV
|
CMPS <= (~FETCH[0][0] | (FETCH[3] == DIN[15:8])) & (FETCH[2] == DIN[7:0]); // early EQ test for CMPS
|
CMPS <= (~FETCH[0][0] | (FETCH[3] == DIN[15:8])) & (FETCH[2] == DIN[7:0]); // early EQ test for CMPS
|
SCAS <= (~FETCH[0][0] | (AX[15:8] == DIN[15:8])) & (AX[7:0] == DIN[7:0]); // early EQ test for SCAS
|
SCAS <= (~FETCH[0][0] | (AX[15:8] == DIN[15:8])) & (AX[7:0] == DIN[7:0]); // early EQ test for SCAS
|
|
RCOUT <= COUT;
|
|
DIVIRQ <= ~|STAGE[6:3] & DIVC & (~STAGE[2] | (~DIVSGN & IDIV)) & (&STAGE[1:0]); // DIV stage4, div loop
|
|
AAMIRQ <= ~|STAGE[6:2] & DIVC & (STAGE[1:0] == 2'b01); // AAM stage2, div
|
end
|
end
|
|
|
always @(ISEL, FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5])
|
always @(ISEL, FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5])
|
case(ISEL)
|
case(ISEL)
|
2'b00: DIMM1 = {FETCH[2], FETCH[1]};
|
2'b00: DIMM1 = {FETCH[2], FETCH[1]};
|
| Line 341... |
Line 354... |
3'b110: ISIZEI = 6;
|
3'b110: ISIZEI = 6;
|
default: ISIZEI = 5;
|
default: ISIZEI = 5;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,
|
always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, RCOUT, DIVEND, DIVIRQ, AAMIRQ, QSGN, CMPS, SCAS,
|
WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, FIN, IDIV, AX) begin
|
WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, FIN, IDIV, AX) begin
|
WORD = FETCH[0][0];
|
WORD = FETCH[0][0];
|
BASEL = FETCH[0][1] | &MOD;
|
BASEL = FETCH[0][1] | &MOD;
|
RASEL = FETCH[0][1] ? REG : RM; // destination
|
RASEL = FETCH[0][1] ? REG : RM; // destination
|
BBSEL = {1'b0, !FETCH[0][1] | &MOD};
|
BBSEL = {1'b0, !FETCH[0][1] | &MOD};
|
| Line 363... |
Line 376... |
MREQ = 1'b1;
|
MREQ = 1'b1;
|
WR = 1'b0;
|
WR = 1'b0;
|
ISIZE = 3'bxxx;
|
ISIZE = 3'bxxx;
|
IPWSEL = 1'b1; // IP + ISIZE
|
IPWSEL = 1'b1; // IP + ISIZE
|
IFETCH = 1'b1;
|
IFETCH = 1'b1;
|
|
IORQ = 1'b0;
|
status = 6'b00x0xx;
|
status = 6'b00x0xx;
|
|
|
DISP16 = MOD == 2'b10 || NOBP;
|
DISP16 = MOD == 2'b10 || NOBP;
|
NOBP = {MOD, RM} == 5'b00110;
|
NOBP = {MOD, RM} == 5'b00110;
|
HALT = 1'b0;
|
HALT = 1'b0;
|
| Line 425... |
Line 439... |
ALUOP = 31; // PASS B
|
ALUOP = 31; // PASS B
|
EAC = 4'b0110;
|
EAC = 4'b0110;
|
DISEL = 2'b00;
|
DISEL = 2'b00;
|
ASEL = 1'b0;
|
ASEL = 1'b0;
|
AEXT = 1'b0;
|
AEXT = 1'b0;
|
MREQ = 1'b1;
|
|
WR = FETCH[0][1];
|
WR = FETCH[0][1];
|
WE[1:0] = WRBIT; // IP, RASEL_HI/RASEL_LO
|
WE[1:0] = WRBIT; // IP, RASEL_HI/RASEL_LO
|
ISIZE = 3;
|
ISIZE = 3;
|
NOBP = 1'b1;
|
NOBP = 1'b1;
|
end
|
end
|
| Line 686... |
Line 699... |
RASEL = 3'b000; // AX/AL
|
RASEL = 3'b000; // AX/AL
|
WE[1:0] = {WORD, 1'b1}; // RASEL_HI, RASEL_LO
|
WE[1:0] = {WORD, 1'b1}; // RASEL_HI, RASEL_LO
|
DISEL = 2'b00; //DIN
|
DISEL = 2'b00; //DIN
|
MREQ = 1'b0;
|
MREQ = 1'b0;
|
ISIZE = FETCH[0][3] ? 1 : 2;
|
ISIZE = FETCH[0][3] ? 1 : 2;
|
EAC = 4'b1111;
|
IORQ = 1'b1;
|
NULLSEG = 1'b1;
|
// EAC = 4'b1111;
|
|
// NULLSEG = 1'b1;
|
end
|
end
|
// -------------------------------- out --------------------------------
|
// -------------------------------- out --------------------------------
|
16: begin
|
16: begin
|
DOSEL = 2'b11; // AX
|
DOSEL = 2'b11; // AX
|
MREQ = 1'b0;
|
MREQ = 1'b0;
|
WR = 1'b1;
|
WR = 1'b1;
|
ISIZE = FETCH[0][3] ? 1 : 2;
|
ISIZE = FETCH[0][3] ? 1 : 2;
|
EAC = 4'b1111;
|
IORQ = 1'b1;
|
NULLSEG = 1'b1;
|
// EAC = 4'b1111;
|
|
// NULLSEG = 1'b1;
|
end
|
end
|
// -------------------------------- xlat --------------------------------
|
// -------------------------------- xlat --------------------------------
|
17: begin
|
17: begin
|
WORD = 1'b0;
|
WORD = 1'b0;
|
RASEL = 3'b000; // AL
|
RASEL = 3'b000; // AL
|
| Line 899... |
Line 914... |
MREQ = ~&MOD;
|
MREQ = ~&MOD;
|
DISEL = {1'b0, MREQ};
|
DISEL = {1'b0, MREQ};
|
DOSEL = 2'b11;
|
DOSEL = 2'b11;
|
IFETCH = 1'b0;
|
IFETCH = 1'b0;
|
DIVSTAGE = ~QSGN;
|
DIVSTAGE = ~QSGN;
|
|
RASEL = 3'b000; // AX
|
|
ALUOP = 5'b01001; // DEC
|
end
|
end
|
3'b001: begin // stage2, pre dec AX
|
3'b001: begin // stage2, pre dec AX
|
// WORD = 1'b1;
|
// WORD = 1'b1;
|
RASEL = 3'b000; // AX
|
RASEL = 3'b000; // AX
|
WE[1:0] = 2'b11; // RASEL_HI, RASEL_LO
|
WE[1:0] = 2'b11; // RASEL_HI, RASEL_LO
|
ALUOP = 5'b01001; // DEC
|
ALUOP = 5'b01001; // DEC
|
IFETCH = 1'b0;
|
IFETCH = 1'b0;
|
ALUSTAGE = ~(DIVQSGN && FETCH[0][0] && COUT);
|
ALUSTAGE = ~(DIVQSGN && FETCH[0][0] && RCOUT);
|
end
|
end
|
3'b010: begin // stage3, pre dec DX
|
3'b010: begin // stage3, pre dec DX
|
RASEL = 3'b010; // DX
|
RASEL = 3'b010; // DX
|
WE[1:0] = 2'b11; // RASEL_HI, RASEL_LO
|
WE[1:0] = 2'b11; // RASEL_HI, RASEL_LO
|
ALUOP = 5'b01001; // DEC
|
ALUOP = 5'b01001; // DEC
|
| Line 923... |
Line 940... |
ALUOP = {2'b00, DIVSGN ? 3'b000 : 3'b101}; // add/sub
|
ALUOP = {2'b00, DIVSGN ? 3'b000 : 3'b101}; // add/sub
|
ISEL = 2'b01;
|
ISEL = 2'b01;
|
DIVSTAGE = ~DIVEND;
|
DIVSTAGE = ~DIVEND;
|
ALUSTAGE = ~DIVEND | ~DIVQSGN;
|
ALUSTAGE = ~DIVEND | ~DIVQSGN;
|
DIVOP = 1'b1;
|
DIVOP = 1'b1;
|
// IRQ = ~|STAGE[6:3] & DIVC & ~(STAGE[2] & DIVSGN); - DIV bug, fixed 23Dec2012
|
IRQ = DIVIRQ; //~|STAGE[6:3] & DIVC & (~STAGE[2] | (~DIVSGN & IDIV)); // early overflow for positive quotient
|
IRQ = ~|STAGE[6:3] & DIVC & (~STAGE[2] | (~DIVSGN & IDIV)); // early overflow for positive quotient
|
IFETCH = (DIVEND && ~DIVQSGN && ~DIVRSGN) || DIVIRQ;
|
IFETCH = (DIVEND && ~DIVQSGN && ~DIVRSGN) || IRQ;
|
|
end
|
end
|
3'b100: begin // stage5, post inc R
|
3'b100: begin // stage5, post inc R
|
RASEL = WORD ? 3'b010 : 3'b100; // DX/AH
|
RASEL = WORD ? 3'b010 : 3'b100; // DX/AH
|
WE[1:0] = {1'b1, WORD}; // RASEL_HI, RASEL_LO
|
WE[1:0] = {1'b1, WORD}; // RASEL_HI, RASEL_LO
|
ALUOP = 5'b01000; // inc
|
ALUOP = 5'b01000; // inc
|
| Line 1189... |
Line 1205... |
if(!STAGE[0]) begin // stage1, input in TMP16
|
if(!STAGE[0]) begin // stage1, input in TMP16
|
WE[3] = 1'b1; // TMP16
|
WE[3] = 1'b1; // TMP16
|
DISEL = 2'b00; //DIN
|
DISEL = 2'b00; //DIN
|
IFETCH = RCXZ; // REP & CX==0
|
IFETCH = RCXZ; // REP & CX==0
|
MREQ = 1'b0;
|
MREQ = 1'b0;
|
EAC = {~RCXZ, 3'b111};
|
IORQ = ~RCXZ;
|
NULLSEG = 1'b1;
|
// EAC = {~RCXZ, 3'b111};
|
|
// NULLSEG = 1'b1;
|
end else begin // stage2, write TMP16 in ES:[DI], inc/dec DI, dec CX
|
end else begin // stage2, write TMP16 in ES:[DI], inc/dec DI, dec CX
|
RASEL = 3'b111; // DI
|
RASEL = 3'b111; // DI
|
RSSEL = 2'b00; // ES
|
RSSEL = 2'b00; // ES
|
WE[1:0] = 2'b11; // RASEL_HI, RASEL_LO
|
WE[1:0] = 2'b11; // RASEL_HI, RASEL_LO
|
ALUOP = {4'b0100, FLAGS[10]};
|
ALUOP = {4'b0100, FLAGS[10]};
|
| Line 1223... |
Line 1240... |
MREQ = ~RCXZ;
|
MREQ = ~RCXZ;
|
WE[3:0] = IFETCH ? 4'b0000 : 4'b1011; // TMP16, RASEL_HI, RASEL_LO
|
WE[3:0] = IFETCH ? 4'b0000 : 4'b1011; // TMP16, RASEL_HI, RASEL_LO
|
end else begin // stage2, out TMP16 at port DX, dec CX
|
end else begin // stage2, out TMP16 at port DX, dec CX
|
DOSEL = 2'b10; // TMP16
|
DOSEL = 2'b10; // TMP16
|
MREQ = 1'b0;
|
MREQ = 1'b0;
|
EAC = 4'b1111;
|
IORQ = 1'b1;
|
|
// EAC = 4'b1111;
|
WR = 1'b1;
|
WR = 1'b1;
|
IFETCH = NRORCXLE1; // not REP or CX<=1
|
IFETCH = NRORCXLE1; // not REP or CX<=1
|
DECCX = CPUStatus[4];
|
DECCX = CPUStatus[4];
|
REPINT = 1'b1;
|
REPINT = 1'b1;
|
NULLSEG = 1'b1;
|
// NULLSEG = 1'b1;
|
end
|
end
|
ISIZE = IFETCH ? 1 : 0;
|
ISIZE = IFETCH ? 1 : 0;
|
end
|
end
|
// -------------------------------- call/jmp direct near --------------------------------
|
// -------------------------------- call/jmp direct near --------------------------------
|
39: begin // jump long
|
39: begin // jump long
|
| Line 1524... |
Line 1542... |
ALUOP = 5'b00101; // sub
|
ALUOP = 5'b00101; // sub
|
ISEL = 2'b00;
|
ISEL = 2'b00;
|
DIVSTAGE = ~DIVEND;
|
DIVSTAGE = ~DIVEND;
|
ALUSTAGE = ~DIVEND;
|
ALUSTAGE = ~DIVEND;
|
DIVOP = 1'b1;
|
DIVOP = 1'b1;
|
IRQ = ~|STAGE[6:2] & DIVC;
|
IRQ = AAMIRQ;//~|STAGE[6:2] & DIVC;
|
IFETCH = IRQ;
|
IFETCH = AAMIRQ;
|
end
|
end
|
3'b110: begin // stage 3, AH <- AL, TMP16 <- AH
|
3'b110: begin // stage 3, AH <- AL, TMP16 <- AH
|
RASEL = 3'b100; // AH
|
RASEL = 3'b100; // AH
|
BASEL = 1'b1;
|
BASEL = 1'b1;
|
RBSEL = 3'b000; // AL
|
RBSEL = 3'b000; // AL
|
| Line 1626... |
Line 1644... |
end else begin
|
end else begin
|
MREQ = 1'b0;
|
MREQ = 1'b0;
|
ISIZE = 0;
|
ISIZE = 0;
|
IRQ = 1'b1;
|
IRQ = 1'b1;
|
end
|
end
|
|
// -------------------------------- SALC --------------------------------
|
|
55: begin
|
|
RASEL = 3'b000; // dest AL (WORD is default 0)
|
|
BASEL = 1'b0;
|
|
BBSEL = 2'b00;
|
|
ALUOP = 3; // sbb
|
|
MREQ = 1'b0;
|
|
WE[0] = 1'b1; // RASEL_LO
|
|
ISIZE = 1;
|
|
end
|
// -------------------------------- bad opcode/esc --------------------------------
|
// -------------------------------- bad opcode/esc --------------------------------
|
default: begin
|
default: begin
|
MREQ = 1'b0;
|
MREQ = 1'b0;
|
ISIZE = 0;
|
ISIZE = 0;
|
IRQ = 1'b1;
|
IRQ = 1'b1;
|
| Line 1791... |
Line 1818... |
8'b10011011: ICODE = 52; // do nothing
|
8'b10011011: ICODE = 52; // do nothing
|
// -------------------------------- aam --------------------------------
|
// -------------------------------- aam --------------------------------
|
8'b11010100: ICODE = 53;
|
8'b11010100: ICODE = 53;
|
// -------------------------------- reset, irq, nmi, intr --------------------------------
|
// -------------------------------- reset, irq, nmi, intr --------------------------------
|
8'b00001111: ICODE = 54;
|
8'b00001111: ICODE = 54;
|
|
// -------------------------------- SALC --------------------------------
|
|
8'b11010110: ICODE = 55;
|
// -------------------------------- bad opcode/esc --------------------------------
|
// -------------------------------- bad opcode/esc --------------------------------
|
default: ICODE = 55;
|
default: ICODE = 56;
|
endcase
|
endcase
|
end
|
end
|
endfunction
|
endfunction
|
|
|
endmodule
|
endmodule
|
