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Line 51... |
// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
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// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
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// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
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// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
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//
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//
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// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
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// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
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// 23Dec2012 - fixed DIV bug (exception on sign bit)
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// 23Dec2012 - fixed DIV bug (exception on sign bit)
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// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_CPU(
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module Next186_CPU(
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output [19:0] ADDR,
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output [19:0] ADDR,
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| Line 859... |
Line 860... |
end
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end
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end
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end
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3'b100, 3'b101: begin // MUL, IMUL
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3'b100, 3'b101: begin // MUL, IMUL
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ISIZE = ISIZES;
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ISIZE = ISIZES;
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ALUOP = {4'b1000, REG[0]}; // BASEL = FETCH[0][1] = 1
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ALUOP = {4'b1000, REG[0]}; // BASEL = FETCH[0][1] = 1
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WE[4] = 1'b1; // fix MUL/IMUL 8bit flags bug
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case(STAGE[1:0])
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case(STAGE[1:0])
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2'b00: begin // stage1, RA -> TMP16, RB (mem) -> FETCH
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2'b00: begin // stage1, RA -> TMP16, RB (mem) -> FETCH
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MREQ = ~&MOD;
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MREQ = ~&MOD;
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DISEL = {1'b0, MREQ};
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DISEL = {1'b0, MREQ};
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RASEL = 3'b000; // AX
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RASEL = 3'b000; // AX
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DOSEL = 2'b11;
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DOSEL = 2'b11;
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IFETCH = 1'b0;
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IFETCH = 1'b0;
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end
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end
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2'b01: begin // stage2, write AX
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2'b01: begin // stage2, write AX
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WE[1:0] = 2'b11;
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WE[1:0] = 2'b11; // flags, RASEL_HI, RASEL_LO
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RASEL = 3'b000; // AX
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RASEL = 3'b000; // AX
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MREQ = 1'b0;
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MREQ = 1'b0;
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IFETCH = ~FETCH[0][0];
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IFETCH = ~FETCH[0][0];
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end
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end
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2'b10: begin // stage 2, write DX
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2'b10: begin // stage 2, write DX
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WE = 5'b10011;
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WE[1:0] = 2'b11; // flags, RASEL_HI, RASEL_LO
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RASEL = 3'b010; // DX
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RASEL = 3'b010; // DX
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MREQ = 1'b0;
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MREQ = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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