| Line 54... |
Line 54... |
// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
|
// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
|
// 23Dec2012 - fixed DIV bug (exception on sign bit)
|
// 23Dec2012 - fixed DIV bug (exception on sign bit)
|
// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
|
// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
|
// 03Apr2013 - fix RET n alignment bug
|
// 03Apr2013 - fix RET n alignment bug
|
// 04Apr2013 - fix TRAP interrupt acknowledge
|
// 04Apr2013 - fix TRAP interrupt acknowledge
|
|
// 12Apr2013 - fix IDIV when Q=0
|
///////////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////////
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
|
module Next186_CPU(
|
module Next186_CPU(
|
output [19:0] ADDR,
|
output [19:0] ADDR,
|
| Line 105... |
Line 106... |
wire ALUCONT;
|
wire ALUCONT;
|
wire NULLSHIFT;
|
wire NULLSHIFT;
|
wire [1:0]CXZ;
|
wire [1:0]CXZ;
|
wire COUT; // adder carry out
|
wire COUT; // adder carry out
|
wire DIVEXC; // exit carry for unsigned DIV
|
wire DIVEXC; // exit carry for unsigned DIV
|
wire SOUT; // adder sign out
|
|
|
|
// Registers
|
// Registers
|
reg [7:0]FETCH[5:0];
|
reg [7:0]FETCH[5:0];
|
reg [6:0]STAGE = 0;
|
reg [6:0]STAGE = 0;
|
reg [5:0]CPUStatus = 0; //1:0=SR override, 2=override ON/OFF, 3=Z(REP), 4=REP ON/OFF, 5=LOCK
|
reg [5:0]CPUStatus = 0; //1:0=SR override, 2=override ON/OFF, 3=Z(REP), 4=REP ON/OFF, 5=LOCK
|
| Line 243... |
Line 243... |
.ALUCONT(ALUCONT),
|
.ALUCONT(ALUCONT),
|
.NULLSHIFT(NULLSHIFT),
|
.NULLSHIFT(NULLSHIFT),
|
.STAGE(STAGE[2:0]),
|
.STAGE(STAGE[2:0]),
|
.INC2(&DISEL), // when DISEL == 2'b11, inc/dec value is 2 if WORD and 1 if ~WORD
|
.INC2(&DISEL), // when DISEL == 2'b11, inc/dec value is 2 if WORD and 1 if ~WORD
|
.COUT(COUT),
|
.COUT(COUT),
|
.SOUT(SOUT),
|
|
.CLK(CLK)
|
.CLK(CLK)
|
);
|
);
|
|
|
Next186_EA EA (
|
Next186_EA EA (
|
.SP(SP),
|
.SP(SP),
|
| Line 341... |
Line 340... |
default: ISIZEI = 5;
|
default: ISIZEI = 5;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,
|
always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,
|
WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, SOUT, IDIV) begin
|
WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, FIN, IDIV, AX) begin
|
WORD = FETCH[0][0];
|
WORD = FETCH[0][0];
|
BASEL = FETCH[0][1] | &MOD;
|
BASEL = FETCH[0][1] | &MOD;
|
RASEL = FETCH[0][1] ? REG : RM; // destination
|
RASEL = FETCH[0][1] ? REG : RM; // destination
|
BBSEL = {1'b0, !FETCH[0][1] | &MOD};
|
BBSEL = {1'b0, !FETCH[0][1] | &MOD};
|
RBSEL = FETCH[0][1] ? RM : REG; // source
|
RBSEL = FETCH[0][1] ? RM : REG; // source
|
| Line 933... |
Line 932... |
end
|
end
|
default: begin // stage6, post inc Q
|
default: begin // stage6, post inc Q
|
RASEL = 3'b000; // AX/AL
|
RASEL = 3'b000; // AX/AL
|
WE[1:0] = {WORD, 1'b1}; // RASEL_HI, RASEL_LO
|
WE[1:0] = {WORD, 1'b1}; // RASEL_HI, RASEL_LO
|
ALUOP = 5'b01000; // inc
|
ALUOP = 5'b01000; // inc
|
IRQ = SOUT ^ DIVSGN; // overflow for negative quotient
|
// IRQ = SOUT ^ DIVSGN; // overflow for negative quotient - fixed 12Apr2013 - IDIV bug when Q=0
|
|
IRQ = ~(FIN[7] | (FETCH[0][0] ? AX[15] : AX[7])); // overflow for negative quotient
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
default: begin // bad opcode
|
default: begin // bad opcode
|
MREQ = 1'b0;
|
MREQ = 1'b0;
|
