Line 54... |
Line 54... |
// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
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// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
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// 23Dec2012 - fixed DIV bug (exception on sign bit)
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// 23Dec2012 - fixed DIV bug (exception on sign bit)
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// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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// 03Apr2013 - fix RET n alignment bug
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// 03Apr2013 - fix RET n alignment bug
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// 04Apr2013 - fix TRAP interrupt acknowledge
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// 04Apr2013 - fix TRAP interrupt acknowledge
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// 12Apr2013 - fix IDIV when Q=0
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_CPU(
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module Next186_CPU(
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output [19:0] ADDR,
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output [19:0] ADDR,
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Line 105... |
Line 106... |
wire ALUCONT;
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wire ALUCONT;
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wire NULLSHIFT;
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wire NULLSHIFT;
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wire [1:0]CXZ;
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wire [1:0]CXZ;
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wire COUT; // adder carry out
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wire COUT; // adder carry out
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wire DIVEXC; // exit carry for unsigned DIV
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wire DIVEXC; // exit carry for unsigned DIV
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wire SOUT; // adder sign out
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// Registers
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// Registers
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reg [7:0]FETCH[5:0];
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reg [7:0]FETCH[5:0];
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reg [6:0]STAGE = 0;
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reg [6:0]STAGE = 0;
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reg [5:0]CPUStatus = 0; //1:0=SR override, 2=override ON/OFF, 3=Z(REP), 4=REP ON/OFF, 5=LOCK
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reg [5:0]CPUStatus = 0; //1:0=SR override, 2=override ON/OFF, 3=Z(REP), 4=REP ON/OFF, 5=LOCK
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Line 243... |
Line 243... |
.ALUCONT(ALUCONT),
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.ALUCONT(ALUCONT),
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.NULLSHIFT(NULLSHIFT),
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.NULLSHIFT(NULLSHIFT),
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.STAGE(STAGE[2:0]),
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.STAGE(STAGE[2:0]),
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.INC2(&DISEL), // when DISEL == 2'b11, inc/dec value is 2 if WORD and 1 if ~WORD
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.INC2(&DISEL), // when DISEL == 2'b11, inc/dec value is 2 if WORD and 1 if ~WORD
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.COUT(COUT),
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.COUT(COUT),
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.SOUT(SOUT),
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.CLK(CLK)
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.CLK(CLK)
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);
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);
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Next186_EA EA (
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Next186_EA EA (
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.SP(SP),
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.SP(SP),
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Line 341... |
Line 340... |
default: ISIZEI = 5;
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default: ISIZEI = 5;
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endcase
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endcase
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end
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end
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always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,
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always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,
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WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, SOUT, IDIV) begin
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WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, FIN, IDIV, AX) begin
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WORD = FETCH[0][0];
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WORD = FETCH[0][0];
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BASEL = FETCH[0][1] | &MOD;
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BASEL = FETCH[0][1] | &MOD;
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RASEL = FETCH[0][1] ? REG : RM; // destination
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RASEL = FETCH[0][1] ? REG : RM; // destination
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BBSEL = {1'b0, !FETCH[0][1] | &MOD};
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BBSEL = {1'b0, !FETCH[0][1] | &MOD};
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RBSEL = FETCH[0][1] ? RM : REG; // source
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RBSEL = FETCH[0][1] ? RM : REG; // source
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Line 933... |
Line 932... |
end
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end
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default: begin // stage6, post inc Q
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default: begin // stage6, post inc Q
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RASEL = 3'b000; // AX/AL
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RASEL = 3'b000; // AX/AL
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WE[1:0] = {WORD, 1'b1}; // RASEL_HI, RASEL_LO
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WE[1:0] = {WORD, 1'b1}; // RASEL_HI, RASEL_LO
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ALUOP = 5'b01000; // inc
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ALUOP = 5'b01000; // inc
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IRQ = SOUT ^ DIVSGN; // overflow for negative quotient
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// IRQ = SOUT ^ DIVSGN; // overflow for negative quotient - fixed 12Apr2013 - IDIV bug when Q=0
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IRQ = ~(FIN[7] | (FETCH[0][0] ? AX[15] : AX[7])); // overflow for negative quotient
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end
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end
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endcase
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endcase
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end
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end
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default: begin // bad opcode
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default: begin // bad opcode
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MREQ = 1'b0;
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MREQ = 1'b0;
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