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https://opencores.org/ocsvn/next186/next186/trunk
[/] [next186/] [trunk/] [Next186_CPU.v] - Diff between revs 12 and 13
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| Rev 12 |
Rev 13 |
| Line 55... |
Line 55... |
// 23Dec2012 - fixed DIV bug (exception on sign bit)
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// 23Dec2012 - fixed DIV bug (exception on sign bit)
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// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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// 03Apr2013 - fix RET n alignment bug
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// 03Apr2013 - fix RET n alignment bug
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// 04Apr2013 - fix TRAP interrupt acknowledge
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// 04Apr2013 - fix TRAP interrupt acknowledge
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// 12Apr2013 - fix IDIV when Q=0
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// 12Apr2013 - fix IDIV when Q=0
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// 16May2013 - fix PUSHA SP pushed stack value, which should be the one before PUSHA
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_CPU(
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module Next186_CPU(
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output [19:0] ADDR,
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output [19:0] ADDR,
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| Line 601... |
Line 602... |
ALUOP = 31; // PASS B
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ALUOP = 31; // PASS B
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EAC = 4'b1000; // SP - 2
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EAC = 4'b1000; // SP - 2
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DISEL = 2'b10; // ADDR
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DISEL = 2'b10; // ADDR
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WR = 1'b1;
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WR = 1'b1;
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ISIZE = 1;
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ISIZE = 1;
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IFETCH = &STAGE[2:0];
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IFETCH = STAGE[2:0] == 3'b111;
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WE[1:0] = 2'b11; // RASEL_HI, RASEL_LO
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WE[1:0] = 2'b11; // RASEL_HI, RASEL_LO
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BASEL = STAGE[1:0] == 2'b00; // 16May2013 - fix PUSHA SP pushed stack value, which should be the one before PUSHA
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BBSEL[0] = STAGE[2:0] != 3'b100; // SP stage
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end
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end
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// -------------------------------- pop R/M --------------------------------
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// -------------------------------- pop R/M --------------------------------
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11:
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11:
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case(REG)
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case(REG)
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3'b000: begin
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3'b000: begin
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