Line 56... |
Line 56... |
// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
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// 03Apr2013 - fix RET n alignment bug
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// 03Apr2013 - fix RET n alignment bug
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// 04Apr2013 - fix TRAP interrupt acknowledge
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// 04Apr2013 - fix TRAP interrupt acknowledge
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// 12Apr2013 - fix IDIV when Q=0
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// 12Apr2013 - fix IDIV when Q=0
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// 16May2013 - fix PUSHA SP pushed stack value, which should be the one before PUSHA
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// 16May2013 - fix PUSHA SP pushed stack value, which should be the one before PUSHA
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// 25May2013 - generate invalid opcode exception for MOV FS and GS
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_CPU(
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module Next186_CPU(
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output [19:0] ADDR,
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output [19:0] ADDR,
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Line 385... |
Line 386... |
if(FETCH[0][2]) WORD = 1'b1;
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if(FETCH[0][2]) WORD = 1'b1;
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if(FETCH[0][2:1] == 2'b10) BBSEL = 2'b11; // RB = SR
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if(FETCH[0][2:1] == 2'b10) BBSEL = 2'b11; // RB = SR
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ALUOP = 31; // PASS B
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ALUOP = 31; // PASS B
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DISEL = {1'b0, &MOD};
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DISEL = {1'b0, &MOD};
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ASEL = 1'b1;
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ASEL = 1'b1;
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MREQ = ~&MOD;
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IRQ = FETCH[0][2] & FETCH[1][5]; // 25May2013 - generate invalid opcode exception for MOV FS and GS
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MREQ = ~&MOD & ~IRQ;
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WR = MREQ & !FETCH[0][1];
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WR = MREQ & !FETCH[0][1];
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WE = WR ? 5'b00000 : &FETCH[0][2:1] ? {2'b00, FETCH[1][4:3] != 2'b01, 2'b00} : {3'b000, WBIT}; // RSSEL, RASEL_HI/RASEL_LO
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WE = WR | IRQ ? 5'b00000 : &FETCH[0][2:1] ? {2'b00, FETCH[1][4:3] != 2'b01, 2'b00} : {3'b000, WBIT}; // RSSEL, RASEL_HI/RASEL_LO
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ISIZE = ISIZES;
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ISIZE = IRQ ? 0 : ISIZES;
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end
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end
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// -------------------------------- mov IMM to R/M --------------------------------
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// -------------------------------- mov IMM to R/M --------------------------------
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1: begin
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1: begin
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RASEL = RM; // destination
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RASEL = RM; // destination
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BBSEL = 2'b10;
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BBSEL = 2'b10;
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