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[/] [next186/] [trunk/] [Next186_CPU.v] - Diff between revs 13 and 14

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Rev 13 Rev 14
Line 56... Line 56...
// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
// 27Feb2013 - fixed MUL/IMUL 8bit flags bug
// 03Apr2013 - fix RET n alignment bug
// 03Apr2013 - fix RET n alignment bug
// 04Apr2013 - fix TRAP interrupt acknowledge
// 04Apr2013 - fix TRAP interrupt acknowledge
// 12Apr2013 - fix IDIV when Q=0
// 12Apr2013 - fix IDIV when Q=0
// 16May2013 - fix PUSHA SP pushed stack value, which should be the one before PUSHA
// 16May2013 - fix PUSHA SP pushed stack value, which should be the one before PUSHA
 
// 25May2013 - generate invalid opcode exception for MOV FS and GS 
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`timescale 1ns / 1ps
 
 
module Next186_CPU(
module Next186_CPU(
    output [19:0] ADDR,
    output [19:0] ADDR,
Line 385... Line 386...
                                if(FETCH[0][2]) WORD = 1'b1;
                                if(FETCH[0][2]) WORD = 1'b1;
                                if(FETCH[0][2:1] == 2'b10) BBSEL = 2'b11; // RB = SR
                                if(FETCH[0][2:1] == 2'b10) BBSEL = 2'b11; // RB = SR
                                ALUOP = 31;     // PASS B
                                ALUOP = 31;     // PASS B
                                DISEL = {1'b0, &MOD};
                                DISEL = {1'b0, &MOD};
                                ASEL = 1'b1;
                                ASEL = 1'b1;
                                MREQ = ~&MOD;
                                IRQ = FETCH[0][2] & FETCH[1][5]; // 25May2013 - generate invalid opcode exception for MOV FS and GS                                              
 
                                MREQ = ~&MOD & ~IRQ;
                                WR = MREQ & !FETCH[0][1];
                                WR = MREQ & !FETCH[0][1];
                                WE = WR ? 5'b00000 : &FETCH[0][2:1] ? {2'b00, FETCH[1][4:3] != 2'b01, 2'b00} : {3'b000, WBIT};           // RSSEL, RASEL_HI/RASEL_LO
                                WE = WR | IRQ ? 5'b00000 : &FETCH[0][2:1] ? {2'b00, FETCH[1][4:3] != 2'b01, 2'b00} : {3'b000, WBIT};             // RSSEL, RASEL_HI/RASEL_LO
                                ISIZE = ISIZES;
                                ISIZE = IRQ ? 0 : ISIZES;
                        end
                        end
// --------------------------------  mov IMM to R/M  --------------------------------
// --------------------------------  mov IMM to R/M  --------------------------------
                        1: begin
                        1: begin
                                RASEL = RM; // destination
                                RASEL = RM; // destination
                                BBSEL = 2'b10;
                                BBSEL = 2'b10;

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