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https://opencores.org/ocsvn/next186/next186/trunk
[/] [next186/] [trunk/] [Next186_CPU.v] - Diff between revs 14 and 19
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| Rev 14 |
Rev 19 |
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Line 61... |
// 25May2013 - generate invalid opcode exception for MOV FS and GS
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// 25May2013 - generate invalid opcode exception for MOV FS and GS
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_CPU(
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module Next186_CPU(
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output [19:0] ADDR,
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output [20:0] ADDR,
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input [15:0] DIN,
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input [15:0] DIN,
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output [15:0] DOUT,
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output [15:0] DOUT,
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input CLK,
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input CLK,
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input CE,
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input CE,
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input INTR,
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input INTR,
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output wire IORQ,
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output wire IORQ,
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output reg INTA,
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output reg INTA,
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output reg WR,
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output reg WR,
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output reg WORD,
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output reg WORD,
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output LOCK,
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output LOCK,
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output [19:0]IADDR,
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output [20:0]IADDR,
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input [47:0]INSTR,
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input [47:0]INSTR,
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output reg IFETCH,
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output reg IFETCH,
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output FLUSH,
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output FLUSH,
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output reg [2:0]ISIZE,
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output reg [2:0]ISIZE,
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output reg HALT
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output reg HALT
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| Line 263... |
Line 263... |
.ADDR16(ADDR16),
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.ADDR16(ADDR16),
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.EAC(EAC)
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.EAC(EAC)
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);
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);
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assign DOUT = DOSEL[1] ? DOSEL[0] ? AX : TMP16 : DOSEL[0] ? IPADD : ALUOUT;
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assign DOUT = DOSEL[1] ? DOSEL[0] ? AX : TMP16 : DOSEL[0] ? IPADD : ALUOUT;
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assign ADDR = {{NULLSEG ? 16'h0000 : RS} + {4'b0000, ADDR16_SP[15:4]}, ADDR16_SP[3:0]};
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assign ADDR = {{NULLSEG ? 16'h0000 : RS} + {5'b00000, ADDR16_SP[15:4]}, ADDR16_SP[3:0]};
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assign IADDR = {CS + {4'b0000, IPIN[15:4]}, IPIN[3:0]};
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assign IADDR = {CS + {5'b00000, IPIN[15:4]}, IPIN[3:0]};
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assign AIMM1 = ASEL ? {FETCH[3], FETCH[2]} : {FETCH[2], FETCH[1]};
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assign AIMM1 = ASEL ? {FETCH[3], FETCH[2]} : {FETCH[2], FETCH[1]};
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always @(posedge CLK)
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always @(posedge CLK)
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if(CE) begin
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if(CE) begin
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if(SRST) begin // reset
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if(SRST) begin // reset
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