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[/] [next186/] [trunk/] [Next186_CPU.v] - Diff between revs 2 and 3
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//
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//
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// Comments:
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// Comments:
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// This project was developed and tested on a XILINX Spartan3AN board.
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// This project was developed and tested on a XILINX Spartan3AN board.
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//
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//
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// Next186 processor features:
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// Next186 processor features:
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// All 80186 intstructions are implemented according with the 80186 specifications
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// All 80186 intstructions are implemented according with the 80186 specifications (excepting ENTER instruction,
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// which uses always 0 as the second parameter - level).
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// Designed with 2 buses: 16bit/20bit data/data_address and 48bit/20bit instruction/instruction_address.
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// Designed with 2 buses: 16bit/20bit data/data_address and 48bit/20bit instruction/instruction_address.
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// This allows most instructions to be executed in one clock cycle.
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// This allows most instructions to be executed in one clock cycle.
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// In order to couple the CPU unit with a single bus, these sepparate data/instruction buses must be multiplexed by
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// In order to couple the CPU unit with a single bus, these sepparate data/instruction buses must be multiplexed by
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// a dedicated bus interface unit (BIU).
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// a dedicated bus interface unit (BIU).
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// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
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// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
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