| Line 49... |
Line 49... |
// In order to couple the CPU unit with a single bus, these sepparate data/instruction buses must be multiplexed by
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// In order to couple the CPU unit with a single bus, these sepparate data/instruction buses must be multiplexed by
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// a dedicated bus interface unit (BIU).
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// a dedicated bus interface unit (BIU).
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// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
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// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
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// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
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// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
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//
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//
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// 16May2012 - fixed CMPS/SCAS bug when interrupted on the <equal> item
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_CPU(
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module Next186_CPU(
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output [19:0] ADDR,
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output [19:0] ADDR,
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| Line 176... |
Line 177... |
// interrupts
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// interrupts
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wire SAMPLEINT = ~(WE[2] & RASEL[1:0] == 2'b10) & ~status[2] & ~status[4] & ~status[5]; // not load SS, no prefix
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wire SAMPLEINT = ~(WE[2] & RASEL[1:0] == 2'b10) & ~status[2] & ~status[4] & ~status[5]; // not load SS, no prefix
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wire NMIACK = SNMI & ~FNMI; // NMI acknowledged
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wire NMIACK = SNMI & ~FNMI; // NMI acknowledged
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wire INTRACK = FLAGS[9] & (~WE[4] | FIN[9]) & SINTR; // INTR acknowledged (IF and not CLI in progress)
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wire INTRACK = FLAGS[9] & (~WE[4] | FIN[9]) & SINTR; // INTR acknowledged (IF and not CLI in progress)
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wire IACK = IRQ | (SAMPLEINT & (NMIACK | INTRACK)) | (~WE[2] & ~HALT & FLAGS[8]); // interrupt acknowledged
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wire IACK = IRQ | (SAMPLEINT & (NMIACK | INTRACK)) | (~WE[2] & ~HALT & FLAGS[8]); // interrupt acknowledged
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reg CMPS; // early EQ test for CMPS
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reg SCAS; // early EQ test for SCAS
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Next186_Regs REGS (
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Next186_Regs REGS (
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.RASEL(RASEL),
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.RASEL(RASEL),
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.RBSEL(RBSEL),
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.RBSEL(RBSEL),
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.BASEL(BASEL),
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.BASEL(BASEL),
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| Line 288... |
Line 291... |
FETCH[2] <= INSTR[23:16];
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FETCH[2] <= INSTR[23:16];
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FETCH[1] <= INSTR[15:8];
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FETCH[1] <= INSTR[15:8];
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FETCH[0] <= INSTR[7:0];
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FETCH[0] <= INSTR[7:0];
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STAGE <= 0;
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STAGE <= 0;
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CPUStatus[5:0] <= status[5:0];
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CPUStatus[5:0] <= status[5:0];
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TZF <= status[3];
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ICODE1 <= ICODE(INSTR[7:0]);
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ICODE1 <= ICODE(INSTR[7:0]);
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end else begin // no interrupt, no fetch
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end else begin // no interrupt, no fetch
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STAGE <= STAGE + {DIVSTAGE, ALUSTAGE} + 1;
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STAGE <= STAGE + {DIVSTAGE, ALUSTAGE} + 1;
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if(&DOSEL) {FETCH[3], FETCH[2]} <= |DISEL ? DIN : RB;
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if(&DOSEL) {FETCH[3], FETCH[2]} <= |DISEL ? DIN : RB;
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TZF <= FIN[6]; // zero flag for REP
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TZF <= FIN[6]; // zero flag for BOUND
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TLF <= FIN[7] != FIN[11]; // less flag for BOUND
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TLF <= FIN[7] != FIN[11]; // less flag for BOUND
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end
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end
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end
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end
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if(IFETCH & ~status[2] & ~status[4] & ~status[5]) CRTIP <= IPIN; // no prefix
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if(IFETCH & ~status[2] & ~status[4] & ~status[5]) CRTIP <= IPIN; // no prefix
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SRST <= RST; // level detection RST
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SRST <= RST; // level detection RST
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| Line 307... |
Line 309... |
SNMI <= 1'b0;
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SNMI <= 1'b0;
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FNMI <= 1'b0;
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FNMI <= 1'b0;
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end
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end
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if(~|STAGE[1:0]) DIVQSGN <= QSGN;
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if(~|STAGE[1:0]) DIVQSGN <= QSGN;
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RDIVEXC <= DIVOP & DIVEXC & ~IDIV; // bit 8/16 for unsigned DIV
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RDIVEXC <= DIVOP & DIVEXC & ~IDIV; // bit 8/16 for unsigned DIV
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CMPS <= (~FETCH[0][0] | (FETCH[3] == DIN[15:8])) & (FETCH[2] == DIN[7:0]); // early EQ test for CMPS
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SCAS <= (~FETCH[0][0] | (AX[15:8] == DIN[15:8])) & (AX[7:0] == DIN[7:0]); // early EQ test for SCAS
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end
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end
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always @(ISEL, FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5])
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always @(ISEL, FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5])
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case(ISEL)
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case(ISEL)
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2'b00: DIMM1 = {FETCH[2], FETCH[1]};
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2'b00: DIMM1 = {FETCH[2], FETCH[1]};
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| Line 332... |
Line 336... |
3'b110: ISIZEI = 6;
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3'b110: ISIZEI = 6;
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default: ISIZEI = 5;
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default: ISIZEI = 5;
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endcase
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endcase
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end
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end
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always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN,
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always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS,
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WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, SOUT) begin
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WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, SOUT) begin
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WORD = FETCH[0][0];
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WORD = FETCH[0][0];
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BASEL = FETCH[0][1] | &MOD;
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BASEL = FETCH[0][1] | &MOD;
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RASEL = FETCH[0][1] ? REG : RM; // destination
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RASEL = FETCH[0][1] ? REG : RM; // destination
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BBSEL = {1'b0, !FETCH[0][1] | &MOD};
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BBSEL = {1'b0, !FETCH[0][1] | &MOD};
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| Line 1061... |
Line 1065... |
33: begin
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33: begin
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DISP16 = 1'b0;
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DISP16 = 1'b0;
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AEXT = 1'b0;
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AEXT = 1'b0;
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NOBP = 1'b1; // for RSSEL
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NOBP = 1'b1; // for RSSEL
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case(STAGE[1:0])
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case(STAGE[1:0])
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2'b00: begin // stage1, read ES:[DI] in FETCH[2:1], inc/dec DI
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2'b00: begin // stage1, read ES:[DI] in FETCH[3:2], inc/dec DI
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RASEL = 3'b111; // SI
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RASEL = 3'b111; // SI
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RSSEL = 2'b00; // ES
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RSSEL = 2'b00; // ES
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ALUOP = {4'b0100, FLAGS[10]};
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ALUOP = {4'b0100, FLAGS[10]};
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EAC = 4'b0101; // DI+DISP
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EAC = 4'b0101; // DI+DISP
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DISEL = 2'b11; // ALU 16bit
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DISEL = 2'b11; // ALU 16bit
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DOSEL = 2'b11; // read data to FETCH
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DOSEL = 2'b11; // read data to FETCH
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IFETCH = CPUStatus[4] && (~|CXZ || (CPUStatus[3] ^ TZF)); // REP & CX==0
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IFETCH = RCXZ;//(~|CXZ || (CPUStatus[3] ^ TZF)); // REP & CX==0
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MREQ = ~IFETCH;
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MREQ = ~RCXZ;
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WE[1:0] = IFETCH ? 2'b00 : 2'b11; // RASEL_HI, RASEL_LO
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WE[1:0] = IFETCH ? 2'b00 : 2'b11; // RASEL_HI, RASEL_LO
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end
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end
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2'b01: begin // stage2, read DS:[SI] in TMP16, inc/dec SI
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2'b01: begin // stage2, read DS:[SI] in TMP16, inc/dec SI
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RASEL = 3'b110; // DI
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RASEL = 3'b110; // DI
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ALUOP = {4'b0100, FLAGS[10]};
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ALUOP = {4'b0100, FLAGS[10]};
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EAC = 4'b0100; // SI+DISP
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EAC = 4'b0100; // SI+DISP
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DISEL = 2'b11; // ALU 16bit
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DISEL = 2'b11; // ALU 16bit
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IFETCH = 1'b0;
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IFETCH = 1'b0;
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WE[3:0] = 4'b1011; // RASEL_HI, RASEL_LO
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WE[3:0] = 4'b1011; // RASEL_HI, RASEL_LO
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end
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end
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2'b10: begin // stage3, compare TMP16 wit imm, set flags, dec CX
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2'b10: begin // stage3, compare TMP16 with imm, set flags, dec CX
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BASEL = 1'b0; // TMP16
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BASEL = 1'b0; // TMP16
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BBSEL = 2'b10; // imm
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BBSEL = 2'b10; // imm
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ISEL = 2'b01;
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ISEL = 2'b01;
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WE[4] = 1'b1; // flags
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WE[4] = 1'b1; // flags
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ALUOP = 5'b00111; // cmp
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ALUOP = 5'b00111; // cmp
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MREQ = 1'b0;
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MREQ = 1'b0;
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IFETCH = ~CPUStatus[4];
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IFETCH = NRORCXLE1 | (CPUStatus[3] ^ CMPS);
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DECCX = CPUStatus[4];
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DECCX = CPUStatus[4];
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ALUSTAGE = 1'b1;
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ALUSTAGE = 1'b1;
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REPINT = 1'b1;
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REPINT = 1'b1;
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end
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end
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endcase
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endcase
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| Line 1099... |
Line 1103... |
end
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end
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// -------------------------------- (rep)scas --------------------------------
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// -------------------------------- (rep)scas --------------------------------
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34: begin
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34: begin
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DISP16 = 1'b0;
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DISP16 = 1'b0;
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AEXT = 1'b0;
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AEXT = 1'b0;
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NOBP = 1'b1; // for RSSEL (not really necesary, but with it the synthesis generates better speed)
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if(!STAGE[0]) begin // stage1, read ES:[DI] in TMP16, inc/dec DI
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if(!STAGE[0]) begin // stage1, read ES:[DI] in TMP16, inc/dec DI
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RASEL = 3'b111; // DI
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RASEL = 3'b111; // DI
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RSSEL = 2'b00; // ES
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RSSEL = 2'b00; // ES
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ALUOP = {4'b0100, FLAGS[10]};
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ALUOP = {4'b0100, FLAGS[10]};
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EAC = 4'b0101; // DI+DISP
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EAC = 4'b0101; // DI+DISP
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DISEL = 2'b11; // ALU 16bit
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DISEL = 2'b11; // ALU 16bit
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IFETCH = CPUStatus[4] && (~|CXZ || (CPUStatus[3] ^ TZF)); // REP & CX==0
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IFETCH = RCXZ;//(~|CXZ || (CPUStatus[3] ^ TZF)); // REP & CX==0
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MREQ = ~IFETCH;
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MREQ = ~RCXZ;
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WE[3:0] = IFETCH ? 4'b0000 : 4'b1011; // TMP16, RASEL_HI, RASEL_LO
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WE[3:0] = IFETCH ? 4'b0000 : 4'b1011; // TMP16, RASEL_HI, RASEL_LO
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end else begin //stage2, compare AL/AX with TMP16, set flags, dec CX
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end else begin //stage2, compare AL/AX with TMP16, set flags, dec CX
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RASEL = 3'b000; // AL/AX
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RASEL = 3'b000; // AL/AX
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BBSEL = 2'b00; // TMP16
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BBSEL = 2'b00; // TMP16
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WE[4] = 1'b1; // flags
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WE[4] = 1'b1; // flags
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ALUOP = 5'b00111; // cmp
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ALUOP = 5'b00111; // cmp
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MREQ = 1'b0;
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MREQ = 1'b0;
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IFETCH = ~CPUStatus[4];
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IFETCH = NRORCXLE1 | (CPUStatus[3] ^ SCAS);
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DECCX = CPUStatus[4];
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DECCX = CPUStatus[4];
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REPINT = 1'b1;
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REPINT = 1'b1;
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end
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end
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ISIZE = IFETCH ? 1 : 0;
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ISIZE = IFETCH ? 1 : 0;
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end
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end
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