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// a dedicated bus interface unit (BIU).
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// a dedicated bus interface unit (BIU).
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// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
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// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU.
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// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
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// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN
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//
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//
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// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
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// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item
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// 23Dec2012 - fixed DIV bug (exception on sign bit)
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module Next186_CPU(
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module Next186_CPU(
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output [19:0] ADDR,
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output [19:0] ADDR,
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ALUOP = {2'b00, DIVSGN ? 3'b000 : 3'b101}; // add/sub
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ALUOP = {2'b00, DIVSGN ? 3'b000 : 3'b101}; // add/sub
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ISEL = 2'b01;
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ISEL = 2'b01;
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DIVSTAGE = ~DIVEND;
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DIVSTAGE = ~DIVEND;
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ALUSTAGE = ~DIVEND | ~DIVQSGN;
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ALUSTAGE = ~DIVEND | ~DIVQSGN;
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DIVOP = 1'b1;
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DIVOP = 1'b1;
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IRQ = ~|STAGE[6:3] & DIVC & ~(STAGE[2] & DIVSGN); // early overflow for positive quotient
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// IRQ = ~|STAGE[6:3] & DIVC & ~(STAGE[2] & DIVSGN); - DIV bug, fixed 23Dec2012
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IRQ = ~|STAGE[6:3] & DIVC & (~STAGE[2] | (~DIVSGN & IDIV)); // early overflow for positive quotient
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IFETCH = (DIVEND && ~DIVQSGN && ~DIVRSGN) || IRQ;
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IFETCH = (DIVEND && ~DIVQSGN && ~DIVRSGN) || IRQ;
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end
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end
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3'b100: begin // stage5, post inc R
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3'b100: begin // stage5, post inc R
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RASEL = WORD ? 3'b010 : 3'b100; // DX/AH
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RASEL = WORD ? 3'b010 : 3'b100; // DX/AH
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WE[1:0] = {1'b1, WORD}; // RASEL_HI, RASEL_LO
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WE[1:0] = {1'b1, WORD}; // RASEL_HI, RASEL_LO
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