| Line 42... |
Line 42... |
// Next8080 processor features:
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// Next8080 processor features:
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// Fast conditional jump/call/ret takes only 1 T state if not executed
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// Fast conditional jump/call/ret takes only 1 T state if not executed
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// Each CPU machine cycle takes (mainly) one clock T state. This makes this processor over 4 times faster than a 8080 at the same
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// Each CPU machine cycle takes (mainly) one clock T state. This makes this processor over 4 times faster than a 8080 at the same
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// clock frequency (some instructions are up to 10 times faster).
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// clock frequency (some instructions are up to 10 times faster).
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// Only 8080 instructions available (minus DAA, which = CPL) + some extra: JR, DJNZ
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// Only 8080 instructions available (minus DAA, which = CPL) + some extra: JR, DJNZ
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// Only IM0 supported, flags 3 and 5 always 0, opcodes DD, ED, FD, CB treated as NOP
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// Only IM0 supported, flags 3 and 5 always 0, opcodes ED, FD, CB treated as NOP
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// No H and N flags, always 0
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// No H and N flags, always 0
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|
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// Indexed mode: after the new instruction INDEX i8 [0xdd, i8], the next instruction (only) will use (mem+i8) instead of (mem)
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// No interrupt is accepted after INDEX i8. i8 is a signed 8bit value.
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// Indexed mode applies to the following instructions:
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// 02h = ld (bc+i8),a
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// 12h = ld (de+i8),a
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// 22h = ld (hl+i8),a instead of ld (nn),hl. Ex: [0xdd 0xff 0x22] will execute ld (hl-1),a
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// 32h = ld (sp+i8),a instead of ld (nn),a. Ex: [0xdd 0x13 0x32] will execute ld (sp+13h),a
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// 0Ah = ld a,(bc+i8)
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// 1Ah = ld a,(de+i8)
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// 2Ah = ld a,(hl+i8),a instead of ld hl,(nn)
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// 3Ah = ld a,(sp+i8),a instead of ld a,(nn)
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// All the other instructions which uses memory at (hl): ld r,(hl+i8); ld (hl+i8),r; inc (hl+i8); dec (hl+i8); ld (hl+i8),n; op a,(hl);
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// ~450 LUT6
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// ~450 LUT6
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// See NextZ80 for more detais
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// See NextZ80 for more detais
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///////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////
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|
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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| Line 68... |
Line 82... |
output reg HALT,
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output reg HALT,
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output reg M1
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output reg M1
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);
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);
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// connections and registers
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// connections and registers
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reg [1:0] CPUStatus = 0; // 0=HL-HL', 1=EI
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reg [2:0] CPUStatus = 0; // 0=HL-DE, 1=EI, 2-indexed mode
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wire [7:0] ALU8FLAGS;
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wire [7:0] ALU8FLAGS;
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wire [7:0] FLAGS;
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wire [7:0] FLAGS;
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wire [7:0] ALU80;
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wire [7:0] ALU80;
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wire [7:0] ALU81;
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wire [7:0] ALU81;
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wire [15:0]ALU160;
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wire [15:0]ALU160;
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| Line 94... |
Line 108... |
reg [4:0] ALU8OP;
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reg [4:0] ALU8OP;
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reg [2:0] ALU16OP;
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reg [2:0] ALU16OP;
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reg next_stage;
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reg next_stage;
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reg [3:0]REG_WSEL;
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reg [3:0]REG_WSEL;
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reg [3:0]REG_RSEL;
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reg [3:0]REG_RSEL;
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reg [2:0]status; // 0=HL-HL', 1=EI, 2=set EI
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reg [3:0]status; // 0=HL-DE, 1=EI, 2=set EI, 3=set indexed mode
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// FETCH[5:3]: 000 NZ, 001 Z, 010 NC, 011 C, 100 PO, 101 PE, 110 P, 111 M
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// FETCH[5:3]: 000 NZ, 001 Z, 010 NC, 011 C, 100 PO, 101 PE, 110 P, 111 M
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wire [7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};
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wire [7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};
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reg tzf;
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reg tzf;
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reg SRESET = 0;
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reg SRESET = 0;
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reg SINT = 0;
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reg SINT = 0;
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| Line 151... |
Line 165... |
if(SRESET) FETCH <= 9'b110000000;
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if(SRESET) FETCH <= 9'b110000000;
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else
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else
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if(FETCH[8:6] == 3'b110) {FETCH[8:7]} <= 2'b00; // exit RESET state
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if(FETCH[8:6] == 3'b110) {FETCH[8:7]} <= 2'b00; // exit RESET state
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else begin
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else begin
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if(M1) FETCH <= {1'b0, DI};
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if(M1) FETCH <= {1'b0, DI};
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if(!next_stage & SINT & CPUStatus[1] & !status[2]) {FETCH[8:6], FETCH[1:0]} <= {3'b100, HALT, M1}; // INT request
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if(!next_stage & SINT & CPUStatus[1] & !status[2] & !status[3]) {FETCH[8:6], FETCH[1:0]} <= {3'b100, HALT, M1}; // INT request
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end
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end
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if(next_stage) STAGE <= STAGE + 1'b1;
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if(next_stage) STAGE <= STAGE + 1'b1;
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else STAGE <= 0;
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else STAGE <= 0;
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CPUStatus[0] <= CPUStatus[0] ^ status[0];
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CPUStatus[0] <= CPUStatus[0] ^ status[0];
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if(status[2]) CPUStatus[1] <= status[1]; // EI
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if(status[2]) CPUStatus[1] <= status[1]; // EI
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if(!next_stage) CPUStatus[2] <= status[3];
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tzf <= ALU8FLAGS[6];
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tzf <= ALU8FLAGS[6];
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end
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end
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assign opd[0] = FETCH[0] ^ &FETCH[2:1];
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assign opd[0] = FETCH[0] ^ &FETCH[2:1];
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assign opd[2:1] = FETCH[2:1];
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assign opd[2:1] = FETCH[2:1];
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| Line 181... |
Line 196... |
M1 = 1;
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M1 = 1;
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MREQ = 1;
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MREQ = 1;
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WR = 0;
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WR = 0;
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HALT = 0;
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HALT = 0;
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IORQ = 0;
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IORQ = 0;
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status = 3'b000;
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status = 4'b0000;
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case(FETCH[8:6])
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case(FETCH[8:6])
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//------------------------------------------- block 00 ----------------------------------------------------
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//------------------------------------------- block 00 ----------------------------------------------------
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3'b000:
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3'b000:
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| Line 260... |
Line 275... |
// ----------------------- LD (BC) A - LD (DE) A - LD (nn) HL, LD (nn),A --------------------
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// ----------------------- LD (BC) A - LD (DE) A - LD (nn) HL, LD (nn),A --------------------
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// ----------------------- LD A (BC) - LD A (DE) - LD HL (nn), LD A (nn) --------------------
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// ----------------------- LD A (BC) - LD A (DE) - LD HL (nn), LD A (nn) --------------------
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4'b0010, 4'b1010:
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4'b0010, 4'b1010:
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case(STAGE[2:0])
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case(STAGE[2:0])
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3'b000:
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3'b000:
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if(FETCH[5] == 0) begin // LD (BC) A, LD (DE) A - stage1
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if(!FETCH[5] | CPUStatus[2]) begin // LD (BC) A, LD (DE) A - stage1
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if(FETCH[3]) DINW_SEL = 1; // DI
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DINW_SEL = 1; // DI
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else DO_SEL = 2'b00; // ALU80
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DO_SEL = 2'b00; // ALU80
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ALU160_SEL = 0; // regs
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ALU160_SEL = 0; // regs
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if(CPUStatus[2]) ALU16OP = 3; // indexed mode
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WE = {4'b000x, FETCH[3], 1'bx}; // hi
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WE = {4'b000x, FETCH[3], 1'bx}; // hi
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next_stage = 1;
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next_stage = 1;
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REG_WSEL = FETCH[3] ? 4'b011x : 4'b0110; // A
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REG_WSEL = FETCH[3] ? 4'b011x : 4'b0110; // A
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REG_RSEL = {op16, 1'bx};
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REG_RSEL = {op16, 1'bx};
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M1 = 0;
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M1 = 0;
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| Line 279... |
Line 295... |
next_stage = 1;
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next_stage = 1;
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REG_WSEL = 4'b111x;
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REG_WSEL = 4'b111x;
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M1 = 0;
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M1 = 0;
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end
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end
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3'b001:
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3'b001:
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if(FETCH[5] == 0) begin // LD (BC), A, LD (DE), A - stage2
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if(!FETCH[5] | CPUStatus[2]) begin // LD (BC), A, LD (DE), A - stage2
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ALU160_SEL = 1; // pc
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ALU160_SEL = 1; // pc
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WE = 6'b010x00; // PC
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WE = 6'b010x00; // PC
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end else begin // LD (nn),A - LH (nn),HL - stage 2
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end else begin // LD (nn),A - LH (nn),HL - stage 2
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ALU160_SEL = 1; // pc
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ALU160_SEL = 1; // pc
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DINW_SEL = 1; // DI
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DINW_SEL = 1; // DI
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| Line 366... |
Line 382... |
ALU8OP = {3'b010, FETCH[0], 1'b0}; // inc / dec
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ALU8OP = {3'b010, FETCH[0], 1'b0}; // inc / dec
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REG_WSEL = {1'b0, opd[5:3]};
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REG_WSEL = {1'b0, opd[5:3]};
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end else case({STAGE[1:0]})
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end else case({STAGE[1:0]})
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2'b00: begin // (HL) - stage1
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2'b00: begin // (HL) - stage1
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ALU160_SEL = 0; // regs
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ALU160_SEL = 0; // regs
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if(CPUStatus[2]) ALU16OP = 3; // indexed mode
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DINW_SEL = 1; // DI
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DINW_SEL = 1; // DI
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WE = 6'b000001; // lo
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WE = 6'b000001; // lo
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ALU16OP = 3'd0;
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next_stage = 1;
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next_stage = 1;
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REG_WSEL = 4'b011x; // tmpLO
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REG_WSEL = 4'b011x; // tmpLO
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REG_RSEL = 4'b010x; // HL
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REG_RSEL = 4'b010x; // HL
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M1 = 0;
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M1 = 0;
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end
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end
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2'b01: begin // (HL) stage2
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2'b01: begin // (HL) stage2
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DO_SEL = 2'b11; // ALU80OUT
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DO_SEL = 2'b11; // ALU80OUT
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ALU160_SEL = 0; // regs
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ALU160_SEL = 0; // regs
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if(CPUStatus[2]) ALU16OP = 3; // indexed mode
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WE = 6'b100x0x; // flags
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WE = 6'b100x0x; // flags
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ALU8OP = {3'b010, FETCH[0], 1'b0}; // inc / dec
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ALU8OP = {3'b010, FETCH[0], 1'b0}; // inc / dec
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ALU16OP = 3'd0;
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next_stage = 1;
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next_stage = 1;
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REG_WSEL = 4'b0111; // tmpLO
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REG_WSEL = 4'b0111; // tmpLO
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REG_RSEL = 4'b010x; // HL
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REG_RSEL = 4'b010x; // HL
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M1 = 0;
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M1 = 0;
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WR = 1;
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WR = 1;
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| Line 409... |
Line 425... |
WE = 6'b010x00; // PC
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WE = 6'b010x00; // PC
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end
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end
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3'b01_1: begin // (HL) - stage2
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3'b01_1: begin // (HL) - stage2
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DO_SEL = 2'b00; // ALU80
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DO_SEL = 2'b00; // ALU80
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ALU160_SEL = 0; // regs
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ALU160_SEL = 0; // regs
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if(CPUStatus[2]) ALU16OP = 3; // indexed mode
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WE = 6'b000x0x; // nothing
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WE = 6'b000x0x; // nothing
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ALU16OP = 3'd0;
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next_stage = 1;
|
next_stage = 1;
|
REG_WSEL = 4'b0111; // tmpLO
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REG_WSEL = 4'b0111; // tmpLO
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REG_RSEL = 4'b010x; // HL
|
REG_RSEL = 4'b010x; // HL
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M1 = 0;
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M1 = 0;
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WR = 1;
|
WR = 1;
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| Line 472... |
Line 488... |
REG_RSEL = {1'b0, opd[2:0]};
|
REG_RSEL = {1'b0, opd[2:0]};
|
end
|
end
|
3'b0_01: // LD r, (HL) 1st stage
|
3'b0_01: // LD r, (HL) 1st stage
|
begin
|
begin
|
ALU160_SEL = 0; // regs
|
ALU160_SEL = 0; // regs
|
|
if(CPUStatus[2]) ALU16OP = 3; // indexed mode
|
DINW_SEL = 1; // DI
|
DINW_SEL = 1; // DI
|
WE = 6'b000x01; // LO
|
WE = 6'b000x01; // LO
|
ALU16OP = 3'd0; // ADD - NOP
|
|
next_stage = 1;
|
next_stage = 1;
|
REG_WSEL = 4'b011x; // A - tmpLO
|
REG_WSEL = 4'b011x; // A - tmpLO
|
REG_RSEL = 4'b010x; // HL
|
REG_RSEL = 4'b010x; // HL
|
M1 = 0;
|
M1 = 0;
|
end
|
end
|
3'b0_10: // LD (HL), r 1st stage
|
3'b0_10: // LD (HL), r 1st stage
|
begin
|
begin
|
DO_SEL = 0; // ALU80
|
DO_SEL = 0; // ALU80
|
ALU160_SEL = 0; // regs
|
ALU160_SEL = 0; // regs
|
|
if(CPUStatus[2]) ALU16OP = 3; // indexed mode
|
WE = 6'b000x00; // no write
|
WE = 6'b000x00; // no write
|
ALU16OP = 3'd0; // ADD - NOP
|
|
next_stage = 1;
|
next_stage = 1;
|
REG_WSEL = {1'b0, opd[2:0]};
|
REG_WSEL = {1'b0, opd[2:0]};
|
REG_RSEL = 4'b010x; // HL
|
REG_RSEL = 4'b010x; // HL
|
M1 = 0;
|
M1 = 0;
|
WR = 1;
|
WR = 1;
|
| Line 519... |
Line 535... |
REG_WSEL = 4'b0110; // A
|
REG_WSEL = 4'b0110; // A
|
REG_RSEL = {1'b0, opd[2:0]};
|
REG_RSEL = {1'b0, opd[2:0]};
|
end
|
end
|
2'b0_1: // OP r, (HL) 1st stage
|
2'b0_1: // OP r, (HL) 1st stage
|
begin
|
begin
|
ALU160_SEL = 0; // HL
|
ALU160_SEL = 0; // regs
|
|
if(CPUStatus[2]) ALU16OP = 3; // indexed mode
|
DINW_SEL = 1; // DI
|
DINW_SEL = 1; // DI
|
WE = 6'b000x01; // lo
|
WE = 6'b000x01; // lo
|
ALU16OP = 3'd0; // ADD - NOP
|
|
next_stage = 1;
|
next_stage = 1;
|
REG_WSEL = 4'b011x; // A-tmpLO
|
REG_WSEL = 4'b011x; // A-tmpLO
|
REG_RSEL = 4'b010x; // HL
|
REG_RSEL = 4'b010x; // HL
|
M1 = 0;
|
M1 = 0;
|
end
|
end
|
| Line 893... |
Line 909... |
ALU160_SEL = 0; // regs
|
ALU160_SEL = 0; // regs
|
WE = 6'b010x00; // PC
|
WE = 6'b010x00; // PC
|
REG_RSEL = 4'b111x; // tmp7
|
REG_RSEL = 4'b111x; // tmp7
|
end
|
end
|
endcase
|
endcase
|
2'b01, 2'b10, 2'b11: begin // DD - IX, ED, FD - IY
|
2'b01: begin // DD - indexed mode
|
|
ALU160_SEL = 1; // PC
|
|
if(!STAGE[0]) begin
|
|
WE = 6'b010100; // PC, tmpHI
|
|
next_stage = 1;
|
|
M1 = 0;
|
|
end else begin
|
|
WE = 6'b010000; // PC
|
|
status[3] = 1'b1; // set indexed mode
|
|
end
|
|
end
|
|
2'b10, 2'b11: begin // ED, FD - IY
|
ALU160_SEL = 1; // PC
|
ALU160_SEL = 1; // PC
|
WE = 6'b010x00; // PC
|
WE = 6'b010x00; // PC
|
end
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
| Line 1211... |
Line 1238... |
case(SEL)
|
case(SEL)
|
0: RAMSEL = 3'b000; // BC
|
0: RAMSEL = 3'b000; // BC
|
1: RAMSEL = rstatus ? 3'b010 : 3'b001; // HL - DE
|
1: RAMSEL = rstatus ? 3'b010 : 3'b001; // HL - DE
|
2: RAMSEL = rstatus ? 3'b001 : 3'b010; // DE - HL
|
2: RAMSEL = rstatus ? 3'b001 : 3'b010; // DE - HL
|
3: RAMSEL = 3'b011; // A-TL
|
3: RAMSEL = 3'b011; // A-TL
|
4: RAMSEL = 3'b100; // I-R
|
default: RAMSEL = 3'b100; // I-R, tmp SP, zero, temp
|
5: RAMSEL = 3'b100; // tmp SP
|
|
6: RAMSEL = 3'b100; // zero
|
|
7: RAMSEL = 3'b100; // temp
|
|
endcase
|
endcase
|
end
|
end
|
endmodule
|
endmodule
|
|
|
module RAM16X8D_regs(
|
module RAM16X8D_regs(
|
