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[/] [nextz80/] [trunk/] [NextZ80CPU.v] - Diff between revs 12 and 13
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| Rev 12 |
Rev 13 |
| Line 169... |
Line 169... |
if(!SNMI) FNMI <= 0;
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if(!SNMI) FNMI <= 0;
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if(SRESET) FETCH <= 10'b1110000000;
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if(SRESET) FETCH <= 10'b1110000000;
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else
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else
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if(FETCH[9:6] == 4'b1110) {FETCH[9:7]} <= 3'b000; // exit RESET state
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if(FETCH[9:6] == 4'b1110) {FETCH[9:7]} <= 3'b000; // exit RESET state
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else begin
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else begin
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if(M1)
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if(M1 || (fetch98 == 2'b10)) // [DD/FD CB disp op] - M1 is inactive during <op> byte read, but FETCH is performed
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case({MREQ, CPUStatus[9:8]})
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case({MREQ, CPUStatus[9:8]})
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3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: FETCH <= {fetch98, DI};
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3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: FETCH <= {fetch98, DI};
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3'b010: FETCH <= {fetch98, 8'hff}; // IM1 - RST38
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3'b010: FETCH <= {fetch98, 8'hff}; // IM1 - RST38
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3'b011: ; // IM2 - get addrLO
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3'b011: ; // IM2 - get addrLO
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endcase
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endcase
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| Line 904... |
Line 904... |
case({STAGE[0], CPUStatus[4]})
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case({STAGE[0], CPUStatus[4]})
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2'b00, 2'b11: begin
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2'b00, 2'b11: begin
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ALU160_SEL = 1; // PC
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ALU160_SEL = 1; // PC
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WE = 6'b010000; // PC
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WE = 6'b010000; // PC
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fetch98 = 2'b10;
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fetch98 = 2'b10;
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M1 = !CPUStatus[4]; // [DD/FD CB disp op] - M1 is inactive during <op> byte read
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end
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end
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2'b01: begin
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2'b01: begin
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ALU160_SEL = 1; // PC
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ALU160_SEL = 1; // PC
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WE = 6'b010100; // PC, tmpHI
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WE = 6'b010100; // PC, tmpHI
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next_stage = 1;
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next_stage = 1;
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