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Line 35... |
import logging
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import logging
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from nocmodel import *
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from nocmodel import *
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from nocmodel.basicmodels import *
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from nocmodel.basicmodels import *
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# Basic example model with TLM simulation
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# Basic example model with TBM simulation
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# 1. Create the model
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# 1. Create the model
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basicnoc = noc(name="Basic 2x2 NoC example")
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basicnoc = noc(name="Basic 2x2 NoC example")
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Line 59... |
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for r in basicnoc.router_list():
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for r in basicnoc.router_list():
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r.update_ports_info()
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r.update_ports_info()
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r.update_routes_info()
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r.update_routes_info()
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# 2. add tlm support, and configure logging
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# 2. add tbm support, and configure logging
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add_tlm_basic_support(basicnoc, log_file="simulation.log", log_level=logging.DEBUG)
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add_tbm_basic_support(basicnoc, log_file="simulation.log", log_level=logging.DEBUG)
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# 3. Declare generators to put in the TLM simulation
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# 3. Declare generators to put in the TBM simulation
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# set ip_cores functionality as myhdl generators
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# set ip_cores functionality as myhdl generators
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def sourcegen(din, dout, tlm_ref, mydest, data=None, startdelay=100, period=100):
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def sourcegen(din, dout, tbm_ref, mydest, data=None, startdelay=100, period=100):
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# this generator only drives dout
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# this generator only drives dout
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@myhdl.instance
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@myhdl.instance
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def putnewdata():
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def putnewdata():
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datacount = 0
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datacount = 0
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protocol_ref = tlm_ref.ipcore_ref.get_protocol_ref()
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protocol_ref = tbm_ref.ipcore_ref.get_protocol_ref()
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mysrc = tlm_ref.ipcore_ref.router_ref.address
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mysrc = tbm_ref.ipcore_ref.router_ref.address
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tlm_ref.debug("sourcegen: init dout is %s" % repr(dout.val))
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tbm_ref.debug("sourcegen: init dout is %s" % repr(dout.val))
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yield myhdl.delay(startdelay)
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yield myhdl.delay(startdelay)
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while True:
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while True:
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if len(data) == datacount:
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if len(data) == datacount:
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tlm_ref.debug("sourcegen: end of data. waiting for %d steps" % (period*10))
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tbm_ref.debug("sourcegen: end of data. waiting for %d steps" % (period*10))
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yield myhdl.delay(period*10)
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yield myhdl.delay(period*10)
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raise myhdl.StopSimulation("data ended at time %d" % myhdl.now())
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raise myhdl.StopSimulation("data ended at time %d" % myhdl.now())
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dout.next = protocol_ref.newpacket(False, mysrc, mydest, data[datacount])
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dout.next = protocol_ref.newpacket(False, mysrc, mydest, data[datacount])
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tlm_ref.debug("sourcegen: data next element %d dout is %s datacount is %d" % (data[datacount], repr(dout.val), datacount))
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tbm_ref.debug("sourcegen: data next element %d dout is %s datacount is %d" % (data[datacount], repr(dout.val), datacount))
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yield myhdl.delay(period)
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yield myhdl.delay(period)
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datacount += 1
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datacount += 1
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return putnewdata
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return putnewdata
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def checkgen(din, dout, tlm_ref, mysrc, data=None):
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def checkgen(din, dout, tbm_ref, mysrc, data=None):
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# this generator only respond to din
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# this generator only respond to din
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@myhdl.instance
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@myhdl.instance
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def checkdata():
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def checkdata():
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datacount = 0
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datacount = 0
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protocol_ref = tlm_ref.ipcore_ref.get_protocol_ref()
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protocol_ref = tbm_ref.ipcore_ref.get_protocol_ref()
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mydest = tlm_ref.ipcore_ref.router_ref.address
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mydest = tbm_ref.ipcore_ref.router_ref.address
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while True:
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while True:
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yield din
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yield din
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if len(data) > datacount:
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if len(data) > datacount:
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checkdata = din.val["data"]
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checkdata = din.val["data"]
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tlm_ref.debug("checkgen: assert checkdata != data[datacount] => %d != %d [%d]" % (checkdata, data[datacount], datacount))
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tbm_ref.debug("checkgen: assert checkdata != data[datacount] => %d != %d [%d]" % (checkdata, data[datacount], datacount))
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if checkdata != data[datacount]:
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if checkdata != data[datacount]:
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tlm_ref.error("checkgen: value != %d (%d)" % (data[datacount], checkdata))
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tbm_ref.error("checkgen: value != %d (%d)" % (data[datacount], checkdata))
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tlm_ref.debug("checkgen: assert source address != mysrc => %d != %d " % (din.val["src"], mysrc))
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tbm_ref.debug("checkgen: assert source address != mysrc => %d != %d " % (din.val["src"], mysrc))
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if din.val["src"] != mysrc:
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if din.val["src"] != mysrc:
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tlm_ref.error("checkgen: source address != %d (%d)" % (mysrc, din.val["src"]))
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tbm_ref.error("checkgen: source address != %d (%d)" % (mysrc, din.val["src"]))
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tlm_ref.debug("checkgen: assert destination address != mydest => %d != %d " % (din.val["dst"], mydest))
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tbm_ref.debug("checkgen: assert destination address != mydest => %d != %d " % (din.val["dst"], mydest))
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if din.val["dst"] != mydest:
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if din.val["dst"] != mydest:
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tlm_ref.error("checkgen: destination address != %d (%d)" % (mydest, din.val["dst"]))
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tbm_ref.error("checkgen: destination address != %d (%d)" % (mydest, din.val["dst"]))
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datacount += 1
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datacount += 1
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return checkdata
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return checkdata
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# 4. Set test vectors
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# 4. Set test vectors
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R11_testdata = [5, 12, 50, -11, 6, 9, 0, 3, 25]
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R11_testdata = [5, 12, 50, -11, 6, 9, 0, 3, 25]
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R12_testdata = [x*5 for x in R11_testdata]
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R12_testdata = [x*5 for x in R11_testdata]
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# 5. assign generators to ip cores (in TLM model !)
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# 5. assign generators to ip cores (in TBM model !)
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# R11 will send to R22, R12 will send to R21
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# R11 will send to R22, R12 will send to R21
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R11.ipcore_ref.tlm.register_generator(sourcegen, mydest=R22.address, data=R11_testdata, startdelay=10, period=20)
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R11.ipcore_ref.tbm.register_generator(sourcegen, mydest=R22.address, data=R11_testdata, startdelay=10, period=20)
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R12.ipcore_ref.tlm.register_generator(sourcegen, mydest=R21.address, data=R12_testdata, startdelay=15, period=25)
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R12.ipcore_ref.tbm.register_generator(sourcegen, mydest=R21.address, data=R12_testdata, startdelay=15, period=25)
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R21.ipcore_ref.tlm.register_generator(checkgen, mysrc=R12.address, data=R12_testdata)
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R21.ipcore_ref.tbm.register_generator(checkgen, mysrc=R12.address, data=R12_testdata)
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R22.ipcore_ref.tlm.register_generator(checkgen, mysrc=R11.address, data=R11_testdata)
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R22.ipcore_ref.tbm.register_generator(checkgen, mysrc=R11.address, data=R11_testdata)
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# 6. configure simulation and run!
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# 6. configure simulation and run!
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basicnoc.tlmsim.configure_simulation(max_time=1000)
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basicnoc.tbmsim.configure_simulation(max_time=1000)
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print "Starting simulation..."
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print "Starting simulation..."
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basicnoc.tlmsim.run()
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basicnoc.tbmsim.run()
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print "Simulation finished. Pick the results in log files."
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print "Simulation finished. Pick the results in log files."
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# 7. View graphical representation
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# 7. View graphical representation
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draw_noc(basicnoc)
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draw_noc(basicnoc)
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