| Line 35... |
Line 35... |
input data_in_clk_valid,
|
input data_in_clk_valid,
|
input data_out_clk,
|
input data_out_clk,
|
input data_out_clk_valid,
|
input data_out_clk_valid,
|
|
|
//User Interface
|
//User Interface
|
output sata_init,
|
|
output command_layer_ready,
|
output command_layer_ready,
|
output reg busy,
|
output reg sata_busy,
|
input send_sync_escape,
|
input send_sync_escape,
|
input [15:0] user_features,
|
input [15:0] user_features,
|
|
|
//XXX: New Stb
|
//XXX: New Stb
|
input write_data_en,
|
// input write_data_stb,
|
input single_rdwr,
|
// input read_data_stb,
|
input read_data_en,
|
output hard_drive_error,
|
output dev_error,
|
|
|
|
input send_user_command_stb,
|
input execute_command_stb,
|
input soft_reset_en,
|
input command_layer_reset,
|
|
|
output reg pio_data_ready,
|
output reg pio_data_ready,
|
input [7:0] command,
|
input [7:0] hard_drive_command,
|
|
|
input [15:0] sector_count,
|
input [15:0] sector_count,
|
input [47:0] sector_address,
|
input [47:0] sector_address,
|
|
|
input [31:0] user_din,
|
input [31:0] user_din,
|
input user_din_stb,
|
input user_din_stb,
|
output [1:0] user_din_ready,
|
output [1:0] user_din_ready,
|
input [1:0] user_din_activate,
|
input [1:0] user_din_activate,
|
output [23:0] user_din_size,
|
output [23:0] user_din_size,
|
|
output user_din_empty,
|
|
|
output [31:0] user_dout,
|
output [31:0] user_dout,
|
output user_dout_ready,
|
output user_dout_ready,
|
input user_dout_activate,
|
input user_dout_activate,
|
input user_dout_stb,
|
input user_dout_stb,
|
| Line 114... |
Line 113... |
input [47:0] d2h_lba,
|
input [47:0] d2h_lba,
|
input [15:0] d2h_sector_count,
|
input [15:0] d2h_sector_count,
|
input [7:0] d2h_status,
|
input [7:0] d2h_status,
|
input [7:0] d2h_error,
|
input [7:0] d2h_error,
|
|
|
|
output d2h_error_bbk, //Bad Block
|
|
output d2h_error_unc, //Uncorrectable Error
|
|
output d2h_error_mc, //Removable Media Error
|
|
output d2h_error_idnf, //request sector's ID Field could not be found
|
|
output d2h_error_mcr, //Removable Media Error
|
|
output d2h_error_abrt, //Abort (from invalid command, drive not ready, write fault)
|
|
output d2h_error_tk0nf, //Track 0 not found
|
|
output d2h_error_amnf, //Data Address Mark is not found after finding correct ID
|
|
|
|
output d2h_status_bsy, //Set to 1 when drive has access to command block, no other bits are valid when 1
|
|
// Set after reset
|
|
// Set after soft reset (srst)
|
|
// Set immediately after host writes to command register
|
|
output d2h_status_drdy, //Drive is ready to accept command
|
|
output d2h_status_dwf, //Drive Write Fault
|
|
output d2h_status_dsc, //Drive Seek Complete
|
|
output d2h_status_drq, //Data Request, Drive is ready to send data to the host
|
|
output d2h_status_corr, //Correctable Data bit (an error that was encountered but was corrected)
|
|
output d2h_status_idx, //once per disc revolution this bit is set to one then back to zero
|
|
output d2h_status_err, //error bit, if this bit is high check the error flags
|
|
|
//command layer data interface
|
//command layer data interface
|
input t_if_strobe,
|
input t_if_strobe,
|
output [31:0] t_if_data,
|
output [31:0] t_if_data,
|
output t_if_ready,
|
output t_if_ready,
|
| Line 132... |
Line 150... |
output [23:0] t_of_size,
|
output [23:0] t_of_size,
|
|
|
|
|
//Debug
|
//Debug
|
output [3:0] cl_c_state,
|
output [3:0] cl_c_state,
|
output [3:0] cl_w_state,
|
output [3:0] cl_w_state
|
output [3:0] cl_r_state
|
|
|
|
);
|
);
|
|
|
|
|
//Parameters
|
//Parameters
|
parameter IDLE = 4'h0;
|
parameter IDLE = 4'h0;
|
parameter PIO_WAIT_FOR_DATA = 4'h1;
|
parameter PIO_WAIT_FOR_DATA = 4'h1;
|
parameter PIO_WRITE_DATA = 4'h2;
|
parameter PIO_WRITE_DATA = 4'h2;
|
|
|
parameter WAIT_FOR_DATA = 4'h1;
|
|
|
|
parameter WAIT_FOR_DMA_ACT = 4'h1;
|
parameter WAIT_FOR_DMA_ACT = 4'h1;
|
parameter WAIT_FOR_WRITE_DATA = 4'h2;
|
parameter WAIT_FOR_WRITE_DATA = 4'h2;
|
parameter SEND_DATA = 4'h3;
|
parameter SEND_DATA = 4'h3;
|
parameter WAIT_FOR_STATUS = 4'h4;
|
|
|
|
//Registers/Wires
|
//Registers/Wires
|
reg [3:0] cntrl_state;
|
reg [3:0] cntrl_state;
|
reg srst;
|
reg srst;
|
reg [7:0] status;
|
reg [7:0] status;
|
wire idle;
|
wire idle;
|
reg cntrl_send_data_stb;
|
reg cntrl_send_data_stb;
|
reg send_command_stb;
|
reg send_command_stb;
|
reg prev_send_command;
|
|
|
|
wire dev_busy;
|
wire dev_busy;
|
wire dev_data_req;
|
wire dev_data_req;
|
|
|
reg [31:0] reset_count;
|
|
wire reset_timeout;
|
|
|
|
//Read State Machine
|
|
reg [3:0] read_state;
|
|
reg read_data_stb;
|
|
reg single_read_prev;
|
|
|
|
//Write State Machine
|
//Write State Machine
|
reg [3:0] write_state;
|
reg [3:0] write_state;
|
reg write_data_stb;
|
|
reg single_write_prev;
|
|
|
|
reg dma_send_data_stb;
|
reg dma_send_data_stb;
|
reg dma_act_detected;
|
reg dma_act_detected_en;
|
|
|
wire write_data_available;
|
|
reg first_write;
|
|
reg first_read;
|
|
|
|
reg enable_tl_data_ready;
|
reg enable_tl_data_ready;
|
|
|
//Ping Pong FIFOs
|
//Ping Pong FIFOs
|
wire [1:0] if_write_ready;
|
wire [1:0] if_write_ready;
|
wire [1:0] if_write_activate;
|
wire [1:0] if_write_activate;
|
wire [23:0] if_write_size;
|
wire [23:0] if_write_size;
|
wire if_write_strobe;
|
wire if_write_strobe;
|
wire if_starved;
|
|
wire [31:0] if_write_data;
|
wire [31:0] if_write_data;
|
|
|
wire if_read_strobe;
|
wire if_read_strobe;
|
wire if_read_ready;
|
wire if_read_ready;
|
wire if_read_activate;
|
wire if_read_activate;
|
| Line 231... |
Line 229... |
.write_data (if_write_data ),
|
.write_data (if_write_data ),
|
.write_ready (if_write_ready ),
|
.write_ready (if_write_ready ),
|
.write_activate (if_write_activate ),
|
.write_activate (if_write_activate ),
|
.write_fifo_size (if_write_size ),
|
.write_fifo_size (if_write_size ),
|
.write_strobe (if_write_strobe ),
|
.write_strobe (if_write_strobe ),
|
.starved (if_starved ),
|
//.starved (if_starved ),
|
|
.starved (user_din_empty ),
|
|
|
//read side
|
//read side
|
//XXX: This can be different clocks
|
//XXX: This can be different clocks
|
.read_clock (clk ),
|
.read_clock (clk ),
|
.read_strobe (if_read_strobe ),
|
.read_strobe (if_read_strobe ),
|
.read_ready (if_read_ready ),
|
.read_ready (if_read_ready ),
|
.read_activate (if_read_activate ),
|
.read_activate (if_read_activate ),
|
.read_count (if_read_size ),
|
.read_count (if_read_size ),
|
.read_data (if_read_data )
|
.read_data (if_read_data ),
|
|
.inactive ( )
|
);
|
);
|
|
|
|
|
//Output FIFO
|
//Output FIFO
|
ppfifo # (
|
ppfifo # (
|
| Line 260... |
Line 260... |
.write_data (of_write_data ),
|
.write_data (of_write_data ),
|
.write_ready (of_write_ready ),
|
.write_ready (of_write_ready ),
|
.write_activate (of_write_activate ),
|
.write_activate (of_write_activate ),
|
.write_fifo_size (of_write_size ),
|
.write_fifo_size (of_write_size ),
|
.write_strobe (of_write_strobe ),
|
.write_strobe (of_write_strobe ),
|
.starved (out_fifo_starved ),
|
//.starved (out_fifo_starved ),
|
|
.starved ( ),
|
|
|
//read side
|
//read side
|
//XXX: This can be different clocks
|
//XXX: This can be different clocks
|
.read_clock (data_out_clk ),
|
.read_clock (data_out_clk ),
|
.read_strobe (of_read_strobe ),
|
.read_strobe (of_read_strobe ),
|
.read_ready (of_read_ready ),
|
.read_ready (of_read_ready ),
|
.read_activate (of_read_activate ),
|
.read_activate (of_read_activate ),
|
.read_count (of_read_size ),
|
.read_count (of_read_size ),
|
.read_data (of_read_data )
|
.read_data (of_read_data ),
|
|
.inactive ( )
|
);
|
);
|
|
|
|
|
//Asynchronous Logic
|
//Asynchronous Logic
|
//Attach output of Input FIFO to TL
|
//Attach output of Input FIFO to TL
|
| Line 300... |
Line 302... |
|
|
assign if_write_data = user_din;
|
assign if_write_data = user_din;
|
assign if_write_strobe = user_din_stb;
|
assign if_write_strobe = user_din_stb;
|
assign user_din_ready = if_write_ready;
|
assign user_din_ready = if_write_ready;
|
assign if_write_activate = user_din_activate;
|
assign if_write_activate = user_din_activate;
|
//assign user_din_size = if_write_size;
|
assign user_din_size = if_write_size;
|
assign user_din_size = 24'h00800;
|
|
//assign user_din_size = 24'h00400;
|
|
//assign user_din_size = 24'h00200;
|
|
|
|
assign user_dout = of_read_data;
|
assign user_dout = of_read_data;
|
assign user_dout_ready = of_read_ready;
|
assign user_dout_ready = of_read_ready;
|
assign of_read_activate = user_dout_activate;
|
assign of_read_activate = user_dout_activate;
|
assign user_dout_size = of_read_size;
|
assign user_dout_size = of_read_size;
|
assign of_read_strobe = user_dout_stb;
|
assign of_read_strobe = user_dout_stb;
|
|
|
|
assign d2h_status_bsy = d2h_status[7];
|
assign write_data_available = (if_read_ready || if_read_activate) || (if_write_ready != 2'b11);
|
assign d2h_status_drdy = d2h_status[6];
|
|
assign d2h_status_dwf = d2h_status[5];
|
|
assign d2h_status_dsc = d2h_status[4];
|
|
assign d2h_status_drq = d2h_status[3];
|
|
assign d2h_status_corr = d2h_status[2];
|
|
assign d2h_status_idx = d2h_status[1];
|
|
assign d2h_status_err = d2h_status[0];
|
|
|
|
assign d2h_error_bbk = d2h_error[7];
|
|
assign d2h_error_unc = d2h_error[6];
|
|
assign d2h_error_mc = d2h_error[5];
|
|
assign d2h_error_idnf = d2h_error[4];
|
|
assign d2h_error_mcr = d2h_error[3];
|
|
assign d2h_error_abrt = d2h_error[2];
|
|
assign d2h_error_tk0nf = d2h_error[1];
|
|
assign d2h_error_amnf = d2h_error[0];
|
|
|
//Strobes
|
//Strobes
|
assign t_send_command_stb = read_data_stb || write_data_stb || send_command_stb;
|
//assign t_send_command_stb = read_data_stb || write_data_stb || execute_command_stb;
|
|
assign t_send_command_stb = execute_command_stb;
|
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
|
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
|
|
|
//IDLE
|
//IDLE
|
assign idle = (cntrl_state == IDLE) &&
|
assign idle = (cntrl_state == IDLE) &&
|
(read_state == IDLE) &&
|
|
(write_state == IDLE) &&
|
(write_state == IDLE) &&
|
transport_layer_ready;
|
transport_layer_ready;
|
|
|
assign command_layer_ready = idle;
|
assign command_layer_ready = idle;
|
assign sata_init = reset_timeout;
|
|
|
|
assign h2d_command = (write_data_en) ? `COMMAND_DMA_WRITE_EX :
|
|
(read_data_en) ? `COMMAND_DMA_READ_EX :
|
|
(send_user_command_stb) ? command :
|
|
h2d_command;
|
|
|
|
|
assign h2d_command = hard_drive_command;
|
assign h2d_sector_count = sector_count;
|
assign h2d_sector_count = sector_count;
|
assign h2d_lba = (write_data_en) ? (!single_rdwr && !first_write) ? d2h_lba + 1 : sector_address :
|
assign h2d_lba = sector_address;
|
(read_data_en) ? (!single_rdwr && !first_read) ? d2h_lba + 1 : sector_address :
|
|
sector_address;
|
|
|
|
//XXX: The individual bits should be controlled directly
|
//XXX: The individual bits should be controlled directly
|
assign h2d_control = {5'h00, srst, 2'b00};
|
assign h2d_control = {5'h00, srst, 2'b00};
|
//XXX: This should be controlled from a higher level
|
//XXX: This should be controlled from a higher level
|
assign h2d_port_mult = 4'h0;
|
assign h2d_port_mult = 4'h0;
|
//XXX: This should be controlled from a higher level
|
//XXX: This should be controlled from a higher level
|
assign h2d_device = `D2H_REG_DEVICE;
|
assign h2d_device = `D2H_REG_DEVICE;
|
|
|
assign dev_busy = status[`STATUS_BUSY_BIT];
|
assign dev_busy = status[`STATUS_BUSY_BIT];
|
assign dev_data_req = status[`STATUS_DRQ_BIT];
|
assign dev_data_req = status[`STATUS_DRQ_BIT];
|
assign dev_error = status[`STATUS_ERR_BIT];
|
assign hard_drive_error = status[`STATUS_ERR_BIT];
|
|
|
assign cl_c_state = cntrl_state;
|
assign cl_c_state = cntrl_state;
|
assign cl_r_state = read_state;
|
|
assign cl_w_state = write_state;
|
assign cl_w_state = write_state;
|
|
|
assign reset_timeout = (reset_count >= `RESET_TIMEOUT);
|
|
|
|
//Synchronous Logic
|
//Synchronous Logic
|
|
|
//Control State Machine
|
//Control State Machine
|
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
if (rst || (!linkup)) begin
|
if (rst || (!linkup)) begin
|
| Line 371... |
Line 374... |
t_send_control_stb <= 0;
|
t_send_control_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
pio_data_ready <= 0;
|
pio_data_ready <= 0;
|
status <= 0;
|
status <= 0;
|
|
|
prev_send_command <= 0;
|
sata_busy <= 0;
|
send_command_stb <= 0;
|
sync_escape <= 0;
|
|
|
reset_count <= 0;
|
|
busy <= 1;
|
|
end
|
end
|
else begin
|
else begin
|
t_send_control_stb <= 0;
|
t_send_control_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
cntrl_send_data_stb <= 0;
|
pio_data_ready <= 0;
|
pio_data_ready <= 0;
|
send_command_stb <= 0;
|
|
|
|
//Reset Count
|
//Reset Count
|
if (reset_count < `RESET_TIMEOUT) begin
|
|
reset_count <= reset_count + 1;
|
|
end
|
|
if (!reset_timeout) begin
|
|
cntrl_state <= IDLE;
|
|
end
|
|
|
|
//detected the first a user attempting to send a command
|
|
if (send_user_command_stb && !prev_send_command) begin
|
|
prev_send_command <= 1;
|
|
send_command_stb <= 1;
|
|
end
|
|
if (!send_user_command_stb) begin
|
|
prev_send_command <= 0;
|
|
end
|
|
|
|
if (t_d2h_reg_stb) begin
|
if (t_d2h_reg_stb) begin
|
busy <= 0;
|
//Receiving a register strobe from the device
|
|
sata_busy <= 0;
|
h2d_features <= `D2H_REG_FEATURES;
|
h2d_features <= `D2H_REG_FEATURES;
|
end
|
end
|
if (t_send_command_stb || t_send_control_stb || send_user_command_stb) begin
|
/*
|
busy <= 1;
|
if (t_send_command_stb || t_send_control_stb) begin
|
if (send_user_command_stb) begin
|
sata_busy <= 1;
|
|
end
|
|
*/
|
|
if (execute_command_stb) begin
|
h2d_features <= user_features;
|
h2d_features <= user_features;
|
end
|
sata_busy <= 1;
|
end
|
end
|
|
|
case (cntrl_state)
|
case (cntrl_state)
|
IDLE: begin
|
IDLE: begin
|
|
|
//Soft Reset will break out of any flow
|
//Soft Reset will break out of any flow
|
if ((soft_reset_en) && !srst) begin
|
if (command_layer_reset && !srst) begin
|
srst <= 1;
|
srst <= 1;
|
t_send_control_stb <= 1;
|
t_send_control_stb <= 1;
|
reset_count <= 0;
|
|
end
|
end
|
|
|
if (idle) begin
|
if (idle) begin
|
//The only way to transition to another state is if CL is IDLE
|
//The only way to transition to another state is if CL is IDLE
|
|
|
//User Initiated commands
|
//User Initiated commands
|
if (!soft_reset_en && srst && reset_timeout) begin
|
if (!command_layer_reset && srst) begin
|
srst <= 0;
|
srst <= 0;
|
t_send_control_stb <= 1;
|
t_send_control_stb <= 1;
|
end
|
end
|
end
|
end
|
|
|
| Line 473... |
Line 459... |
end
|
end
|
endcase
|
endcase
|
|
|
if (send_sync_escape) begin
|
if (send_sync_escape) begin
|
cntrl_state <= IDLE;
|
cntrl_state <= IDLE;
|
busy <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
//Read State Machine
|
|
always @ (posedge clk) begin
|
|
if (rst || (!linkup)) begin
|
|
read_state <= IDLE;
|
|
sync_escape <= 0;
|
|
read_data_stb <= 0;
|
|
single_read_prev <= 0;
|
|
first_read <= 1;
|
|
end
|
|
else begin
|
|
read_data_stb <= 0;
|
|
sync_escape <= 0;
|
|
|
|
if (!read_data_en) begin
|
|
single_read_prev <= 0;
|
|
end
|
|
|
|
case (read_state)
|
|
IDLE: begin
|
|
if (idle) begin
|
|
sync_escape <= 0;
|
|
//The only way to transition to another state is if CL is IDLE
|
|
if (read_data_en) begin
|
|
if (single_rdwr) begin
|
|
if (!single_read_prev) begin
|
|
single_read_prev <= 1;
|
|
read_data_stb <= 1;
|
|
read_state <= WAIT_FOR_DATA;
|
|
end
|
|
end
|
|
else begin
|
|
//send a request to read data
|
|
read_data_stb <= 1;
|
|
read_state <= WAIT_FOR_DATA;
|
|
end
|
|
end
|
|
else begin
|
|
first_read <= 1;
|
|
end
|
|
end
|
|
end
|
|
WAIT_FOR_DATA: begin
|
|
//This state seems useless because it only sets a value but the state is used to indicate the system is idle or not
|
|
if (t_d2h_data_stb) begin
|
|
first_read <= 0;
|
|
end
|
|
/*
|
|
if (soft_reset_en) begin
|
|
//XXX: Issue a SYNC ESCAPE to cancel a large read request otherwise let it play out
|
|
//sync_escape <= 1;
|
|
end
|
|
*/
|
|
end
|
|
default: begin
|
|
read_state <= IDLE;
|
|
end
|
|
endcase
|
|
|
|
if (soft_reset_en || !reset_timeout || send_sync_escape) begin
|
|
if (read_state != IDLE) begin
|
|
sync_escape <= 1;
|
sync_escape <= 1;
|
end
|
sata_busy <= 0;
|
if (send_sync_escape) begin
|
|
sync_escape <= 1;
|
|
end
|
|
read_state <= IDLE;
|
|
end
|
|
|
|
//If this is received go back to IDLE
|
|
if (t_d2h_reg_stb) begin
|
|
read_state <= IDLE;
|
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//Write State Machine
|
//Write State Machine
|
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
if (rst || (!linkup)) begin
|
if (rst || !linkup) begin
|
write_state <= IDLE;
|
write_state <= IDLE;
|
|
|
dma_send_data_stb <= 0;
|
dma_send_data_stb <= 0;
|
|
|
write_data_stb <= 0;
|
|
single_write_prev <= 0;
|
|
first_write <= 1;
|
|
enable_tl_data_ready <= 0;
|
enable_tl_data_ready <= 0;
|
|
dma_act_detected_en <= 0;
|
dma_act_detected <= 0;
|
|
end
|
end
|
else begin
|
else begin
|
dma_send_data_stb <= 0;
|
dma_send_data_stb <= 0;
|
write_data_stb <= 0;
|
|
|
|
if (enable_tl_data_ready && if_read_activate) begin
|
|
//Closes the loop on the data write feedback
|
|
enable_tl_data_ready <= 0;
|
|
end
|
|
|
|
if (!write_data_en) begin
|
|
single_write_prev <= 0;
|
|
end
|
|
|
|
if (t_dma_activate_stb) begin
|
if (t_dma_activate_stb) begin
|
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
|
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
|
dma_act_detected <= 1;
|
dma_act_detected_en <= 1;
|
end
|
end
|
|
|
case (write_state)
|
case (write_state)
|
IDLE: begin
|
IDLE: begin
|
|
enable_tl_data_ready <= 0;
|
if (idle) begin
|
if (idle) begin
|
//The only way to transition to another state is if CL is IDLE
|
//The only way to transition to another state is if CL is IDLE
|
if (write_data_en) begin
|
//if (write_data_stb) begin
|
if (single_rdwr) begin
|
if (dma_act_detected_en) begin
|
if (!single_write_prev) begin
|
|
single_write_prev <= 1;
|
|
write_state <= WAIT_FOR_DMA_ACT;
|
|
write_data_stb <= 1;
|
|
end
|
|
end
|
|
else begin
|
|
//send a request to write data
|
//send a request to write data
|
write_state <= WAIT_FOR_DMA_ACT;
|
write_state <= WAIT_FOR_DMA_ACT;
|
write_data_stb <= 1;
|
|
end
|
|
end
|
|
else begin
|
|
//reset the the first write when the user deassertes the write_data_en
|
|
first_write <= 1;
|
|
end
|
end
|
end
|
end
|
end
|
end
|
WAIT_FOR_DMA_ACT: begin
|
WAIT_FOR_DMA_ACT: begin
|
if (dma_act_detected) begin
|
if (dma_act_detected_en) begin
|
dma_act_detected <= 0;
|
dma_act_detected_en <= 0;
|
first_write <= 0;
|
|
enable_tl_data_ready <= 1;
|
enable_tl_data_ready <= 1;
|
write_state <= WAIT_FOR_WRITE_DATA;
|
write_state <= WAIT_FOR_WRITE_DATA;
|
end
|
end
|
end
|
end
|
WAIT_FOR_WRITE_DATA: begin
|
WAIT_FOR_WRITE_DATA: begin
|
if (if_read_activate) begin
|
if (if_read_activate) begin
|
|
enable_tl_data_ready <= 0;
|
write_state <= SEND_DATA;
|
write_state <= SEND_DATA;
|
end
|
end
|
end
|
end
|
SEND_DATA: begin
|
SEND_DATA: begin
|
if (transport_layer_ready) begin
|
if (transport_layer_ready) begin
|
//Send the Data FIS
|
//Send the Data FIS
|
dma_send_data_stb <= 1;
|
dma_send_data_stb <= 1;
|
write_state <= WAIT_FOR_DMA_ACT;
|
dma_act_detected_en <= 0;
|
end
|
|
end
|
|
WAIT_FOR_STATUS: begin
|
|
if (t_d2h_reg_stb) begin
|
|
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
end
|
end
|
default: begin
|
default: begin
|
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
endcase
|
endcase
|
|
|
|
|
if (soft_reset_en || !reset_timeout) begin
|
//if (command_layer_reset || !reset_timeout) begin
|
|
if (command_layer_reset) begin
|
//Break out of the normal flow and return to IDLE
|
//Break out of the normal flow and return to IDLE
|
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
if (t_d2h_reg_stb) begin
|
if (t_d2h_reg_stb) begin
|
//Whenever I read a register transfer from the device I need to go back to IDLE
|
//Whenever I read a register transfer from the device I need to go back to IDLE
|
| Line 654... |
Line 535... |
write_state <= IDLE;
|
write_state <= IDLE;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
