| Line 47... |
Line 47... |
input detect_hold,
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input detect_hold,
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input detect_cont,
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input detect_cont,
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input detect_xrdy_xrdy,
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input detect_xrdy_xrdy,
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output [31:0] tx_dout,
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output [31:0] tx_dout,
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output tx_isk,
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output tx_is_k,
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input [31:0] rx_din,
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input [31:0] rx_din,
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input [3:0] rx_isk,
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input [3:0] rx_is_k,
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output reg read_strobe,
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output reg read_strobe,
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output reg [31:0] read_data,
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output reg [31:0] read_data,
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input read_ready,
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input read_ready,
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output read_start,
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output read_start,
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| Line 89... |
Line 89... |
reg send_holda;
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reg send_holda;
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reg send_sync;
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reg send_sync;
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//CRC
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//CRC
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//XXX: Tie the CRC_EN to an incomming data dword
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//XXX: Tie the CRC_EN to an incomming data dword
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wire crc_en;
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wire [31:0] crc_din;
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wire [31:0] crc_din;
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wire [31:0] crc_dout;
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reg crc_data;
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reg crc_check;
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reg [31:0] prev_crc;
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reg [31:0] prev_crc;
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reg [31:0] prev_data;
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reg [31:0] prev_data;
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wire data_valid;
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wire data_valid;
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reg first_dword;
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reg first_dword;
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| Line 108... |
Line 104... |
wire descr_en;
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wire descr_en;
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wire [31:0] descr_din;
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wire [31:0] descr_din;
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wire [31:0] descr_dout;
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wire [31:0] descr_dout;
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//SubModules
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//SubModules
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crc c (
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.rst (rst || idle ),
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.clk (clk ),
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.en (crc_en ),
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.din (crc_din ),
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.dout (crc_dout )
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);
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scrambler descr (
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scrambler descr (
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.rst (rst || idle),
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.rst (rst || idle),
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.clk (clk ),
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.clk (clk ),
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.prim_scrambler (0 ),
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.prim_scrambler (1'b0 ),
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.en (descr_en ),
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.en (descr_en ),
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.din (rx_din ),
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.din (rx_din ),
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.dout (descr_dout )
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.dout (descr_dout )
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);
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);
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| Line 138... |
Line 126... |
(send_hold) ? `PRIM_HOLD :
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(send_hold) ? `PRIM_HOLD :
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(send_sync) ? `PRIM_SYNC :
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(send_sync) ? `PRIM_SYNC :
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(send_holda) ? `PRIM_HOLDA :
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(send_holda) ? `PRIM_HOLDA :
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`PRIM_SYNC;
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`PRIM_SYNC;
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assign tx_isk = ( send_r_rdy ||
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assign tx_is_k = ( send_r_rdy ||
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send_r_ip ||
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send_r_ip ||
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send_r_err ||
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send_r_err ||
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send_r_ok ||
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send_r_ok ||
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send_hold ||
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send_hold ||
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send_holda ||
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send_holda ||
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| Line 151... |
Line 139... |
assign crc_din = (data_scrambler_en) ? descr_dout : rx_din;
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assign crc_din = (data_scrambler_en) ? descr_dout : rx_din;
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//assign read_data = (read_strobe) ? rx_din : 32'h0;
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//assign read_data = (read_strobe) ? rx_din : 32'h0;
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assign read_finished = detect_eof;
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assign read_finished = detect_eof;
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assign read_start = detect_sof;
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assign read_start = detect_sof;
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assign data_valid = (state == READ) &&
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assign data_valid = (state == READ) &&
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(rx_isk == 0) &&
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(rx_is_k == 0) &&
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(!detect_hold) &&
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(!detect_hold) &&
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(!detect_holda) &&
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(!detect_holda) &&
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(!detect_align);
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(!detect_align);
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assign crc_en = data_valid;
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assign descr_en = (data_scrambler_en && (detect_sof || data_valid));
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assign descr_en = (data_scrambler_en && (detect_sof || data_valid));
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assign descr_din = (data_valid) ? rx_din : 32'h00000000;
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assign descr_din = (data_valid) ? rx_din : 32'h00000000;
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//assign crc_ok = (prev_data == prev_crc);
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//assign crc_ok = (prev_data == prev_crc);
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assign lax_r_state = state;
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assign lax_r_state = state;
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