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[/] [nysa_sata/] [trunk/] [sim/] [faux_sata_hd.v] - Diff between revs 2 and 3

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Rev 2 Rev 3
Line 29... Line 29... 
input               rst,              //reset
 
input               rst,              //reset
 
input               clk,
 
input               clk,
 
 
 
 
 
//Data Interface
 
//Data Interface
 
output      [31:0]  tx_dout,
 
output      [31:0]  tx_dout,
 
output      [3:0]   tx_isk,
 
output      [3:0]   tx_is_k,
 
output              tx_set_elec_idle,
 
output              tx_set_elec_idle,
 
output              rx_byte_is_aligned,
 
output              rx_byte_is_aligned,
 
 
 
 
 
input       [31:0]  rx_din,
 
input       [31:0]  rx_din,
 
input       [3:0]   rx_isk,
 
input       [3:0]   rx_is_k,
 
input               rx_is_elec_idle,
 
input               rx_is_elec_idle,
 
 
 
 
 
input               comm_reset_detect,
 
input               comm_reset_detect,
 
input               comm_wake_detect,
 
input               comm_wake_detect,
 
 
 
 
Line 141... Line 141... 
);
 
);
 
 
 
 
 
//Parameters
 
//Parameters
 
//Registers/Wires
 
//Registers/Wires
 
wire        [31:0]  phy_tx_dout;
 
wire        [31:0]  phy_tx_dout;
 
wire                phy_tx_isk;
 
wire                phy_tx_is_k;
 
 
 
 
 
wire        [31:0]  sll_tx_dout;
 
wire        [31:0]  sll_tx_dout;
 
wire                sll_tx_isk;
 
wire                sll_tx_is_k;
 
 
 
 
 
wire                ll_ready;
 
wire                ll_ready;
 
wire                ll_write_start;
 
wire                ll_write_start;
 
wire                ll_write_finished;
 
wire                ll_write_finished;
 
wire                ll_write_strobe;
 
wire                ll_write_strobe;
Line 278... Line 278... 
  .rst                  (rst                    ),
 
  .rst                  (rst                    ),
 
  .clk                  (clk                    ),
 
  .clk                  (clk                    ),
 
 
 
 
 
  //incomming/output data
 
  //incomming/output data
 
  .tx_dout              (phy_tx_dout            ),
 
  .tx_dout              (phy_tx_dout            ),
 
  .tx_isk               (phy_tx_isk             ),
 
  .tx_is_k              (phy_tx_is_k            ),
 
  .tx_set_elec_idle     (tx_set_elec_idle       ),
 
  .tx_set_elec_idle     (tx_set_elec_idle       ),
 
 
 
 
 
  .rx_din               (rx_din                 ),
 
  .rx_din               (rx_din                 ),
 
  .rx_isk               (rx_isk                 ),
 
  .rx_is_k              (rx_is_k                ),
 
  .rx_is_elec_idle      (rx_is_elec_idle        ),
 
  .rx_is_elec_idle      (rx_is_elec_idle        ),
 
  .rx_byte_is_aligned   (rx_byte_is_aligned     ),
 
  .rx_byte_is_aligned   (rx_byte_is_aligned     ),
 
 
 
 
 
  .comm_reset_detect    (comm_reset_detect      ),
 
  .comm_reset_detect    (comm_reset_detect      ),
 
  .comm_wake_detect     (comm_wake_detect       ),
 
  .comm_wake_detect     (comm_wake_detect       ),
Line 301... Line 301... 
);
 
);
 
 
 
 
 
sata_link_layer fsll (
 
sata_link_layer fsll (
 
  .rst                  (rst || !hd_ready       ),
 
  .rst                  (rst || !hd_ready       ),
 
  .clk                  (clk                    ),
 
  .clk                  (clk                    ),
 
  .prim_scrambler_en    (1                      ),
 
  .prim_scrambler_en    (1'b1                   ),
 
  .data_scrambler_en    (data_scrambler_en      ),
 
  .data_scrambler_en    (data_scrambler_en      ),
 
 
 
 
 
  .link_layer_ready     (ll_ready               ),
 
  .link_layer_ready     (ll_ready               ),
 
  .sync_escape          (0                      ),
 
  .sync_escape          (1'b0                   ),
 
  .hold                 (dbg_hold               ),
 
  .hold                 (dbg_hold               ),
 
 
 
 
 
  //Transport Layer Interface
 
  //Transport Layer Interface
 
  .write_start          (ll_write_start         ),
 
  .write_start          (ll_write_start         ),
 
  .write_strobe         (ll_write_strobe        ),
 
  .write_strobe         (ll_write_strobe        ),
Line 330... Line 330... 
 
 
 
 
  //Phy Layer
 
  //Phy Layer
 
  .phy_ready            (phy_ready              ),
 
  .phy_ready            (phy_ready              ),
 
  .platform_ready       (hd_ready               ),
 
  .platform_ready       (hd_ready               ),
 
  .tx_dout              (sll_tx_dout            ),
 
  .tx_dout              (sll_tx_dout            ),
 
  .tx_isk               (sll_tx_isk             ),
 
  .tx_is_k              (sll_tx_is_k            ),
 
 
 
 
 
  .rx_din               (rx_din                 ),
 
  .rx_din               (rx_din                 ),
 
  .rx_isk               (rx_isk                 ),
 
  .rx_is_k              (rx_is_k                ),
 
  .is_device            (1                      )
 
  .is_device            (1'b1                   )
 
);
 
);
 
 
 
 
 
faux_sata_hd_transport  ftl (
 
faux_sata_hd_transport  ftl (
 
  .rst                  (rst || !hd_ready       ),
 
  .rst                  (rst || !hd_ready       ),
 
  .clk                  (clk                    ),
 
  .clk                  (clk                    ),
Line 417... Line 417... 
 
 
 
 
 
 
 
 
);
 
);
 
 
 
 
 
faux_hd_command_layer fcl(
 
faux_hd_command_layer fcl(
 
  .rst                  (rst                    ),
 
  .rst                  (rst || !hd_ready       ),
 
  .clk                  (clk                    ),
 
  .clk                  (clk                    ),
 
 
 
 
 
  .command_layer_ready  (command_layer_ready    ),
 
  .command_layer_ready  (command_layer_ready    ),
 
 
 
 
 
  .hd_read_from_host    (hd_read_from_host      ),
 
  .hd_read_from_host    (hd_read_from_host      ),
Line 484... Line 484... 
  .cl_state             (cl_state               )
 
  .cl_state             (cl_state               )
 
 
 
 
 
);
 
);
 
 
 
 
 
assign                  tx_dout         = !phy_ready ? phy_tx_dout : sll_tx_dout;
 
assign                  tx_dout         = !phy_ready ? phy_tx_dout : sll_tx_dout;
 
assign                  tx_isk[3:1]     =  3'b000;
 
assign                  tx_is_k[3:1]     =  3'b000;
 
assign                  tx_isk[0]       = !phy_ready ? phy_tx_isk  : sll_tx_isk;
 
assign                  tx_is_k[0]       = !phy_ready ? phy_tx_is_k  : sll_tx_is_k;
 
 
 
 
 
 
 
 
 
//Debug
 
//Debug
 
//assign                ll_write_start        = (dbg_ll_en) ? dbg_ll_write_start  : t_write_start;
 
//assign                ll_write_start        = (dbg_ll_en) ? dbg_ll_write_start  : t_write_start;
 
//assign                ll_write_data         = (dbg_ll_en) ? dbg_ll_write_data   : t_write_data;
 
//assign                ll_write_data         = (dbg_ll_en) ? dbg_ll_write_data   : t_write_data;

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