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[/] [nysa_sata/] [trunk/] [sim/] [faux_sata_hd_command_layer.v] - Diff between revs 2 and 3

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Rev 2	Rev 3
Line 102...	Line 102...
`parameter READ_DATA = 4'h4;`	`parameter READ_DATA = 4'h4;`
`parameter SEND_DATA = 4'h5;`	`parameter SEND_DATA = 4'h5;`
`parameter READ_IN_PROGRESS = 4'h6;`	`parameter READ_IN_PROGRESS = 4'h6;`
`parameter SEND_STATUS = 4'h7;`	`parameter SEND_STATUS = 4'h7;`

	`parameter SLEEP_LENGTH = 100;`

`//Registers/Wires`	`//Registers/Wires`
`reg [3:0] state = SLEEP_START;`	`reg [3:0] state = SLEEP_START;`
`wire idle;`	`wire idle;`

`reg [8:0] byte_count = 0;`	`reg [8:0] byte_count = 0;`
`reg [15:0] sector_count = 0;`	`reg [16:0] sector_count = 0;`
`reg [15:0] sector_size = 16'h0000;`	`reg [16:0] sector_size = 16'h0000;`

`reg [15:0] sleep_count = 0;`	`reg [15:0] sleep_count = 0;`
`reg [15:0] sleep_size = 1000;`


`wire soft_reset;`	`wire soft_reset;`

`//Asynchronous Logic`	`//Asynchronous Logic`
Line 150...	Line 151...

`sector_count <= 0;`	`sector_count <= 0;`
`sector_size <= 1000;`	`sector_size <= 1000;`

`sleep_count <= 0;`	`sleep_count <= 0;`
`sleep_size <= 1000;`



`pio_transfer_count <= 0;`	`pio_transfer_count <= 0;`
`pio_direction <= 0;`	`pio_direction <= 0;`
Line 179...	Line 179...
`send_data_stb <= 0;`	`send_data_stb <= 0;`
`send_pio_stb <= 0;`	`send_pio_stb <= 0;`
`send_dev_bits_stb <= 0;`	`send_dev_bits_stb <= 0;`

`if (soft_reset) begin`	`if (soft_reset) begin`
	`if (soft_reset) begin`
	`$display ("Reset from soft reset");`
	`end`
`state <= SLEEP_START;`	`state <= SLEEP_START;`
`sleep_count <= 0;`	`sleep_count <= 0;`
`sleep_size <= 1000;`
`end`	`end`

`case (state)`	`case (state)`
`SLEEP_START: begin`	`SLEEP_START: begin`
`if (sleep_count < sleep_size) begin`	`if (sleep_count < SLEEP_LENGTH) begin`
`sleep_count <= sleep_count + 1;`	`sleep_count <= sleep_count + 1;`
`end`	`end`
`else begin`	`else begin`
`state <= SEND_DIAGNOSTICS;`	`state <= SEND_DIAGNOSTICS;`
`end`	`end`
`end`	`end`
`SEND_DIAGNOSTICS: begin`	`SEND_DIAGNOSTICS: begin`
	`$display ("Send Diagnostics");`
`send_reg_stb <= 1;`	`send_reg_stb <= 1;`
`state <= IDLE;`	`state <= IDLE;`
`end`	`end`
`IDLE: begin`	`IDLE: begin`
`if (h2d_reg_stb) begin`	`if (h2d_reg_stb) begin`
`if (h2d_cmd_bit) begin`	`if (h2d_cmd_bit) begin`
`d2h_lba <= h2d_lba;`	`d2h_lba <= h2d_lba;`
`d2h_sector_count <= h2d_sector_count;`	`d2h_sector_count <= h2d_sector_count;`

	`if (h2d_sector_count == 0) begin`
	`sector_size <= 17'h10000;`
	`end`
	`else begin`
`sector_size <= h2d_sector_count;`	`sector_size <= h2d_sector_count;`
	`end`

`case (h2d_command)`	`case (h2d_command)`
`COMMAND_DMA_READ_EX: begin	`COMMAND_DMA_READ_EX: begin
`//send_data_stb <= 1;`	`//send_data_stb <= 1;`
`sector_count <= 0;`	`sector_count <= 0;`
`sector_size <= h2d_sector_count;`
`state <= SEND_DATA;`	`state <= SEND_DATA;`
`end`	`end`
`COMMAND_DMA_WRITE_EX: begin	`COMMAND_DMA_WRITE_EX: begin
`send_dma_act_stb <= 1;`	`send_dma_act_stb <= 1;`
`sector_count <= 0;`	`sector_count <= 0;`
`sector_size <= h2d_sector_count;`
`state <= DMA_READY;`	`state <= DMA_READY;`
`end`	`end`
`default: begin`	`default: begin`
`//unrecognized command`	`//unrecognized command`
`$display ("fcl: Unrecognized command from host");`	`$display ("fcl: Unrecognized command from host");`
Line 283...	Line 289...
`end`	`end`
`default: begin`	`default: begin`
`$display ("fcl: Entered illegal state, restart");`	`$display ("fcl: Entered illegal state, restart");`
`state <= SLEEP_START;`	`state <= SLEEP_START;`
`sleep_count <= 0;`	`sleep_count <= 0;`
`sleep_size <= 1000;`
`end`	`end`
`endcase`	`endcase`
`end`	`end`
`end`	`end`

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[/] [nysa_sata/] [trunk/] [sim/] [faux_sata_hd_command_layer.v] - Diff between revs 2 and 3