| Line 29... |
Line 29... |
input rst, //reset
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input rst, //reset
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input clk,
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input clk,
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//Data Interface
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//Data Interface
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output reg [31:0] tx_dout,
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output reg [31:0] tx_dout,
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output reg tx_isk,
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output reg tx_is_k,
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output reg tx_set_elec_idle,
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output reg tx_set_elec_idle,
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output reg rx_byte_is_aligned,
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output reg rx_byte_is_aligned,
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input [31:0] rx_din,
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input [31:0] rx_din,
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input [3:0] rx_isk,
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input [3:0] rx_is_k,
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input rx_is_elec_idle,
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input rx_is_elec_idle,
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input comm_reset_detect,
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input comm_reset_detect,
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input comm_wake_detect,
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input comm_wake_detect,
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| Line 85... |
Line 85... |
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//Asynchronous Logic
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//Asynchronous Logic
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assign lax_state = state;
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assign lax_state = state;
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assign align_detected = ((rx_isk > 0) && (rx_din == `PRIM_ALIGN));
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assign align_detected = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
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assign dialtone_detected = ((rx_isk == 0) && (rx_din == `DIALTONE));
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assign dialtone_detected = ((rx_is_k == 0) && (rx_din == `DIALTONE));
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assign timeout = (timer == 0);
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assign timeout = (timer == 0);
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assign phy_ready = (state == READY);
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assign phy_ready = (state == READY);
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//Synchronous Logic
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//Synchronous Logic
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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if (rst) begin
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if (rst) begin
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state <= IDLE;
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state <= IDLE;
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tx_dout <= 0;
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tx_dout <= 0;
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tx_isk <= 0;
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tx_is_k <= 0;
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tx_set_elec_idle <= 1;
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tx_set_elec_idle <= 1;
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timer <= 0;
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timer <= 0;
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hd_ready <= 0;
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hd_ready <= 0;
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rx_byte_is_aligned <= 0;
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rx_byte_is_aligned <= 0;
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align_count <= 0;
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align_count <= 0;
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| Line 116... |
Line 116... |
timer <= timer - 1;
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timer <= timer - 1;
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end
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end
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if ((comm_reset_detect) && (state > WAIT_FOR_NO_RESET)) begin
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if ((comm_reset_detect) && (state > WAIT_FOR_NO_RESET)) begin
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$display("faux_sata_hd: Asynchronous RESET detected");
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$display("faux_sata_hd: Asynchronous RESET detected");
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state <= IDLE;
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align_count <= 0;
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hd_ready <= 0;
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state <= WAIT_FOR_NO_RESET;
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end
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end
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case (state)
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case (state)
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IDLE: begin
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IDLE: begin
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align_count <= 0;
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align_count <= 0;
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| Line 135... |
Line 137... |
WAIT_FOR_NO_RESET: begin
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WAIT_FOR_NO_RESET: begin
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if (!comm_reset_detect) begin
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if (!comm_reset_detect) begin
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//host stopped sending reset
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//host stopped sending reset
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$display("faux_sata_hd: RESET deasserted");
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$display("faux_sata_hd: RESET deasserted");
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hd_ready <= 0;
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hd_ready <= 0;
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tx_set_elec_idle <= 1;
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state <= SEND_INIT;
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state <= SEND_INIT;
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end
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end
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end
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end
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SEND_INIT: begin
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SEND_INIT: begin
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//XXX: I may need to send more than one of these
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//XXX: I may need to send more than one of these
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| Line 168... |
Line 169... |
$display ("faux_sata_hd: stop sending WAKE");
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$display ("faux_sata_hd: stop sending WAKE");
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state <= WAIT_FOR_DIALTONE;
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state <= WAIT_FOR_DIALTONE;
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end
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end
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WAIT_FOR_DIALTONE: begin
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WAIT_FOR_DIALTONE: begin
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if (dialtone_detected) begin
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if (dialtone_detected) begin
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$display ("faul_sata_hd: detected dialtone");
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$display ("faux_sata_hd: detected dialtone");
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state <= SEND_ALIGN;
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state <= SEND_ALIGN;
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end
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end
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end
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end
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SEND_ALIGN: begin
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SEND_ALIGN: begin
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$display ("faul_sata_hd: send aligns");
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$display ("faux_sata_hd: send aligns");
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tx_set_elec_idle <= 0;
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tx_set_elec_idle <= 0;
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tx_dout <= `PRIM_ALIGN;
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tx_dout <= `PRIM_ALIGN;
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tx_isk <= 1;
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tx_is_k <= 1;
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state <= WAIT_FOR_ALIGN;
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state <= WAIT_FOR_ALIGN;
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timer <= 32'h`INITIALIZE_TIMEOUT;
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timer <= 32'h`INITIALIZE_TIMEOUT;
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rx_byte_is_aligned <= 1;
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rx_byte_is_aligned <= 1;
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end
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end
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WAIT_FOR_ALIGN: begin
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WAIT_FOR_ALIGN: begin
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tx_is_k <= 1;
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tx_dout <= `PRIM_ALIGN;
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rx_byte_is_aligned <= 1;
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rx_byte_is_aligned <= 1;
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//$display ("faux_sata_hd: waiting for aligns...");
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//$display ("rx din: %h, k: %h", rx_din, rx_is_k);
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if (align_detected) begin
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if (align_detected) begin
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$display ("faux_sata_hd: detected ALIGN primitive from host");
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$display ("faux_sata_hd: detected ALIGN primitive from host");
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$display ("faux_sata_hd: Ready");
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$display ("faux_sata_hd: Ready");
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tx_dout <= `PRIM_ALIGN;
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tx_dout <= `PRIM_ALIGN;
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tx_isk <= 1;
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tx_is_k <= 1;
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timer <= 0;
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timer <= 0;
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state <= READY;
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state <= READY;
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end
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end
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else if (timeout) begin
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else if (timeout) begin
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$display ("faux_sata_hd: Timeout while waiting for an alignment from the host");
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$display ("faux_sata_hd: Timeout while waiting for an alignment from the host");
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| Line 199... |
Line 204... |
end
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end
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end
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end
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READY: begin
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READY: begin
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hd_ready <= 1;
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hd_ready <= 1;
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rx_byte_is_aligned <= 1;
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rx_byte_is_aligned <= 1;
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tx_isk <= 1;
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tx_is_k <= 1;
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tx_dout <= `PRIM_SYNC;
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tx_dout <= `PRIM_SYNC;
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if (align_count == 255) begin
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if (align_count == 255) begin
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tx_dout <= `PRIM_ALIGN;
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tx_dout <= `PRIM_ALIGN;
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state <= SEND_FIRST_ALIGNMENT;
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state <= SEND_FIRST_ALIGNMENT;
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end
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end
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end
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end
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SEND_FIRST_ALIGNMENT: begin
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SEND_FIRST_ALIGNMENT: begin
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rx_byte_is_aligned <= 1;
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rx_byte_is_aligned <= 1;
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tx_isk <= 1;
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tx_is_k <= 1;
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tx_dout <= `PRIM_ALIGN;
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tx_dout <= `PRIM_ALIGN;
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state <= SEND_SECOND_ALIGNMENT;
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state <= SEND_SECOND_ALIGNMENT;
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end
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end
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SEND_SECOND_ALIGNMENT: begin
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SEND_SECOND_ALIGNMENT: begin
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rx_byte_is_aligned <= 1;
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rx_byte_is_aligned <= 1;
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tx_isk <= 1;
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tx_is_k <= 1;
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tx_dout <= `PRIM_ALIGN;
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tx_dout <= `PRIM_ALIGN;
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state <= READY;
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state <= READY;
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end
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end
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default: begin
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default: begin
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$display ("faux_sata_hd: In undefined state!");
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$display ("faux_sata_hd: In undefined state!");
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