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https://opencores.org/ocsvn/ofdm/ofdm/trunk
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Rev 4 |
| Line 66... |
Line 66... |
mem_ready : in std_logic;
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mem_ready : in std_logic;
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Iin : in std_logic_vector(11 downto 0);
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Iin : in std_logic_vector(11 downto 0);
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mem_block : out std_logic;
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mem_block : out std_logic;
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wen : in std_logic;
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wen : in std_logic;
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addrin_in : in std_logic_vector(6 downto 0);
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addrin_in : in std_logic_vector(6 downto 0);
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txserial : out std_logic;
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txserial : out std_logic
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);
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);
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end component;
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end component;
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component BUFGP
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component BUFGP
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port (I: in std_logic; O: out std_logic);
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port (I: in std_logic; O: out std_logic);
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Line 96... |
rst => rst,
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rst => rst,
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serial => rxserial,
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serial => rxserial,
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Iout => Iin,
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Iout => Iin,
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Output_enable => Output_enable,
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Output_enable => Output_enable,
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addrout_out => address_read
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addrout_out => address_read
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--pmem_block => mem_block_tx ,
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--pmem_ready => mem_ready_tx ,
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--pwen => wen_tx ,
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--paddress => address_tx ,
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--pi => i_tx ,
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--pq => q_tx
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);
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);
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txrx_1 : txrx
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txrx_1 : txrx
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port map (
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port map (
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clk => clk,
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clk => clk,
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Line 118... |
mem_ready => mem_ready,
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mem_ready => mem_ready,
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Iin => Iin(13 downto 2),
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Iin => Iin(13 downto 2),
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mem_block => mem_block,
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mem_block => mem_block,
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wen => wen,
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wen => wen,
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addrin_in => address_write,
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addrin_in => address_write,
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txserial => txserial,
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txserial => txserial
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pIout => Iout_rx ,
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);
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pQout => Qout_rx ,
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pOutput_enable => Output_enable_rx,
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paddrout_out => addrout_out_rx );
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end modem;
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end modem;
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No newline at end of file
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No newline at end of file
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