URL
https://opencores.org/ocsvn/ofdm/ofdm/trunk
[/] [ofdm/] [trunk/] [vhdl/] [modem.vhd] - Diff between revs 2 and 4
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 2 |
Rev 4 |
Line 66... |
Line 66... |
mem_ready : in std_logic;
|
mem_ready : in std_logic;
|
Iin : in std_logic_vector(11 downto 0);
|
Iin : in std_logic_vector(11 downto 0);
|
mem_block : out std_logic;
|
mem_block : out std_logic;
|
wen : in std_logic;
|
wen : in std_logic;
|
addrin_in : in std_logic_vector(6 downto 0);
|
addrin_in : in std_logic_vector(6 downto 0);
|
txserial : out std_logic;
|
txserial : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component BUFGP
|
component BUFGP
|
port (I: in std_logic; O: out std_logic);
|
port (I: in std_logic; O: out std_logic);
|
Line 96... |
Line 96... |
rst => rst,
|
rst => rst,
|
serial => rxserial,
|
serial => rxserial,
|
Iout => Iin,
|
Iout => Iin,
|
Output_enable => Output_enable,
|
Output_enable => Output_enable,
|
addrout_out => address_read
|
addrout_out => address_read
|
--pmem_block => mem_block_tx ,
|
|
--pmem_ready => mem_ready_tx ,
|
|
--pwen => wen_tx ,
|
|
--paddress => address_tx ,
|
|
--pi => i_tx ,
|
|
--pq => q_tx
|
|
|
|
);
|
);
|
|
|
txrx_1 : txrx
|
txrx_1 : txrx
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
Line 125... |
Line 118... |
mem_ready => mem_ready,
|
mem_ready => mem_ready,
|
Iin => Iin(13 downto 2),
|
Iin => Iin(13 downto 2),
|
mem_block => mem_block,
|
mem_block => mem_block,
|
wen => wen,
|
wen => wen,
|
addrin_in => address_write,
|
addrin_in => address_write,
|
txserial => txserial,
|
txserial => txserial
|
pIout => Iout_rx ,
|
);
|
pQout => Qout_rx ,
|
|
pOutput_enable => Output_enable_rx,
|
|
paddrout_out => addrout_out_rx );
|
|
|
|
end modem;
|
end modem;
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.